Assignment of Assignor's Interest

Recorded: 2019-08-06 Pages: 3

Assignor

VERISILICON, INC.

Executed: 2004-10-19

Assignee

VERISILICON HOLDINGS CO., LTD.

4699 OLD IRONSIDES DRIVE, SUITE 270, SANTA CLARA, CALIFORNIA, 95054

Covered Property (1)

Automatic Circuit Design Method with a Cell Library Providing Transistor Size Information

Patent: 7,114,134 →

Application: 10/856,732 →

Publication: US 2005/0278660

Related Assignments (2)

Other recorded transfers of the patent in this record — the chain of ownership.