Patent Assignment
Reel/Frame 050261/0464
Assignment of Assignor's Interest
Recorded: 2019-09-04
Pages: 5
Assignors
LIN, JIEFENG JEFF
Executed: 2019-05-21
LIN, CHIH-YUNG
Executed: 2019-05-21
YU, DIAN-SHEG
Executed: 2019-05-21
YANG, HSIAO-LAN
Executed: 2019-05-21
LIAW, JHON JHY
Executed: 2019-05-21
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
8, LI-HSIN RD. 6, HSINCHU SCIENCE PARK, HSINCHU, 300-78, TAIWAN
Covered Property
(1)
Reconfiguring Layout and Sizing for Transistor Components to Simultaneously Optimize Logic Devices and Non-Logic Devices