Patent Assignment
Reel/Frame 050696/0683
Assignment of Assignor's Interest
Recorded: 2019-10-14
Pages: 3
Assignors
SALIK, RACHID
Executed: 2019-09-24
HSU, CHIN-CHANG
Executed: 2019-09-24
WU, CHENG-CHI
Executed: 2019-09-17
CHEN, CHIEN-WEN
Executed: 2019-09-19
YANG, WEN-JU
Executed: 2019-09-17
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
NO. 8, LI-HSIN ROAD, VI, HSINCHU SCIENCE PARK, HSINCHU, TAIWAN
Covered Property
(1)
Integrated Circuit Layout Validation Using Machine Learning