Patent Assignment
Reel/Frame 056729/0519
SHORT FORM INTELLECTUAL PROPERTY SECURITY AGREEMENT
Recorded: 2021-06-30
Received: 2021-06-30
Pages: 12
Assignor
UNIQUIFY, INC.
Executed: 2021-06-30
Assignee
NEWLIGHT CAPITAL LLC, AS SERVICER
525 MIDDLEFIELD ROAD, SUITE 250, MENLO PARK, CA, 94025, UNITED STATES
Covered Applications
(34)
CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS
App. No. 17/074,403
→
DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD
App. No. 16/909,871
→
DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD
App. No. 16/584,600
→
DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD
App. No. 16/296,025
→
CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS
App. No. 16/254,436
→
DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD
App. No. 16/049,693
→
DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD
App. No. 15/996,365
→
METHOD FOR CALIBRATING CAPTURING READ DATA IN A READ DATA PATH FOR A DDR MEMORY INTERFACE CIRCUIT
App. No. 15/926,902
→
CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS
App. No. 15/853,568
→
METHOD FOR CALIBRATING CAPTURING READ DATA IN A READ DATA PATH FOR A DDR MEMORY INTERFACE CIRCUIT
App. No. 15/722,209
→
Multiple Gating Modes and Half-Frequency Dynamic Calibration for DDR Memory Controllers
App. No. 15/249,188
→
CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS
App. No. 15/237,473
→
CIRCUIT FOR DYNAMICALLY ADAPTIVE BIT-LEVELING BY INCREMENTAL SAMPLING, JITTER DETECTION, AND EXCEPTION HANDLING
App. No. 15/078,939
→
Multiple Gating Modes and Half-Frequency Dynamic Calibration for DDR Memory Controllers
App. No. 14/882,226
→
CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS
App. No. 14/850,792
→
METHODS FOR CALIBRATING A READ DATA PATH FOR A MEMORY INTERFACE
App. No. 14/752,903
→
HALF-FREQUENCY DYNAMIC CALIBRATION FOR DDR MEMORY CONTROLLERS
App. No. 62/063,136
→
METHODS FOR DYNAMICALLY ADAPTIVE BIT-LEVELING BY SWEEP SAMPLING WITH AUTOMATIC JITTER AVOIDANCE
App. No. 14/273,455
→
METHODS FOR DYNAMICALLY ADAPTIVE BIT-LEVELING BY INCREMENTAL SAMPLING, JITTER DETECTION, AND EXCEPTION HANDLING
App. No. 14/273,416
→
CIRCUITS FOR DYNAMICALLY ADAPTIVE BIT-LEVELING BY SWEEP SAMPLING WITH AUTOMATIC JITTER AVOIDANCE
App. No. 14/273,438
→
CONTINUOUS ADAPTIVE TRAINING FOR DATA INTERFACE TIMING CALIBRATION
PCTPCTUS2014024818
→
CONTINUOUS ADAPTIVE TRAINING FOR DATA INTERFACE TIMING CALIBRATION
App. No. 14/205,208
→
METHOD FOR OPERATING A CIRCUIT INCLUDING A TIMING CALIBRATION FUNCTION
App. No. 14/205,254
→
DATA INTERFACE CIRCUIT FOR CAPTURING RECEIVED DATA BITS INCLUDING CONTINUOUS CALIBRATION
App. No. 14/205,239
→
METHOD FOR OPERATING A DATA INTERFACE CIRCUIT WHERE A CALIBRATION CONTROLLER CONTROLS BOTH A MISSION PATH AND A REFERENCE PATH
App. No. 14/205,225
→
Method of Application Memory Preservation for Dynamic Calibration of Memory Interfaces
App. No. 14/152,807
→
Application Memory Preservation for Dynamic Calibration of Memory Interfaces
App. No. 14/152,902
→
MEMORY INTERFACE CIRCUITS INCLUDING CALIBRATION FOR CAS LATENCY COMPENSATION IN A PLURALITY OF BYTE LANES
App. No. 14/081,806
→
METHODS FOR OPERATING A MEMORY INTERFACE CIRCUIT INCLUDING CALIBRATION FOR CAS LATENCY COMPENSATION IN A PLURALITY OF BYTE LANES
App. No. 14/081,897
→
Dynamically Calibrated DDR Memory Controller
App. No. 14/023,630
→
DYNAMICALLY ADAPTIVE BIT-LEVELING FOR DATA INTERFACES
App. No. 13/797,200
→
CONTINUOUS ADAPTIVE TRAINING FOR DATA INTERFACE TIMING CALIBRATION
App. No. 61/777,648
→
DYNAMICALLY CALIBRATED DDR MEMORY CONTROLLER
App. No. 13/172,740
→
DDR MEMORY CONTROLLER
App. No. 12/157,081
→