Patent Assignment
Reel/Frame 058214/0380
GRANT OF SECURITY INTEREST IN PATENT RIGHTS
Recorded: 2021-11-19
Received: 2021-11-19
Pages: 36
Assignors
ATMEL CORPORATION
Executed: 2021-11-17
MICROCHIP TECHNOLOGY INCORPORATED
Executed: 2021-11-17
MICROSEMI CORPORATION
Executed: 2021-11-17
MICROSEMI STORAGE SOLUTIONS, INC.
Executed: 2021-11-17
SILICON STORAGE TECHNOLOGY, INC.
Executed: 2021-11-17
Assignee
JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
10 S DEARBORN ST., CHICAGO, IL, 60603, UNITED STATES
Covered Applications
(100)
LEAD FRAMES FOR SEMICONDUCTOR PACKAGES WITH INCREASED RELIABILITY AND RELATED SEMICONDUCTOR DEVICE PACKAGES AND METHODS
App. No. 17/314,535
→
METAL-INSULATOR-METAL (MIM) CAPACITOR AND THIN-FILM RESISTOR (TFR) FORMED IN AN INTEGRATED CIRCUIT STRUCTURE
App. No. 17/308,270
→
METAL-OXIDE-METAL (MOM) CAPACITORS FOR INTEGRATED CIRCUIT MONITORING
App. No. 17/306,019
→
SYSTEMS AND METHODS TO REMOVE INPUT VOLTAGE DEPENDENCY IN A POWER CONVERTER
App. No. 17/244,882
→
SYSTEM AND METHOD FOR SYNCHRONIZING NODES IN A NETWORK DEVICE
App. No. 17/242,493
→
FLASH MEMORY CELL AND ASSOCIATED HIGH VOLTAGE ROW DECODER
App. No. 17/239,397
→
Method and Apparatus for Reading a Flash Memory Device
App. No. 17/234,993
→
INTEGRATED CIRCUIT E-FUSE HAVING AN E-FUSE ELEMENT PROVIDING A DIFFUSION BARRIER FOR UNDERLYING E-FUSE TERMINALS
App. No. 17/233,311
→
ELECTRONIC FUSE (E-FUSE) WITH DISPLACEMENT-PLATED E-FUSE TERMINALS
App. No. 17/233,367
→
THIN-FILM RESISTOR (TFR) HAVING A TFR ELEMENT PROVIDING A DIFFUSION BARRIER FOR UNDERLYING TFR HEADS
App. No. 17/233,285
→
THIN-FILM RESISTOR (TFR) WITH DISPLACEMENT-PLATED TFR HEADS
App. No. 17/233,342
→
SEMICONDUCTOR DEVICE PACKAGES INCLUDING MULTIPLE LEAD FRAMES AND RELATED METHODS
App. No. 17/301,864
→
Automatic Threshold Adjustment for USB Power Delivery to Work with Cables Out of Specification
App. No. 17/229,083
→
AMPLIFIED CHARGE CANCELLATION IN A TOUCH SENSOR, AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 17/301,744
→
PROVISIONING HEADLESS WIFI DEVICES AND RELATED SYSTEMS, METHODS AND DEVICES
App. No. 17/301,522
→
Tswitch with Reduced Current Leakage
App. No. 63/169,571
→
DIGITAL OUTPUT MECHANISMS FOR ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
App. No. 17/219,352
→
Method and apparatus for determining when actual wear of a flash memory device differs from reliability states for the flash memory device
App. No. 17/213,675
→
CIRCUITRY FOR AUTONOMOUSLY MEASURING ANALOG SIGNALS AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 17/301,105
→
MULTI-BIAS MODE CURRENT CONVEYOR, CONFIGURING A MULTI-BIAS MODE CURRENT CONVEYOR, TOUCH SENSING SYSTEMS INCLUDING A MULTI-BIAS MODE CURRENT CONVEYOR, AND RELATED SYSTEMS, METHODS AND DEVICES
App. No. 17/301,080
→
LOW CONNECTION COUNT INTERFACE WAKE SOURCE COMMUNICATION ACCORDING TO 10SPE LOCAL AND REMOTE WAKE AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 17/301,094
→
RECOGNIZING AN OBJECT USING CAPACITIVE SENSING
App. No. 17/249,925
→
DC-DC Converter With Improved Line Transient Rejection
App. No. 17/198,911
→
METHODS AND SYSTEMS FOR DETERMINING A NOISE-ROBUST ACQUISITION CONFIGURATION FOR OPERATING A SENSOR SYSTEM
App. No. 17/198,860
→
ARCHITECTURES FOR STORING AND RETRIEVING SYSTEM DATA IN A NON-VOLATILE MEMORY SYSTEM
App. No. 17/199,383
→
Set-While-Verify Circuit And Reset-While Verify Circuit For Resistive Random Access Memory Cells
App. No. 17/199,243
→
LOW-LATENCY MACSEC AUTHENTICATION
App. No. 17/193,172
→
PROGRAMMING ANALOG NEURAL MEMORY CELLS IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK
App. No. 17/191,392
→
CONCURRENT WRITE AND VERIFY OPERATIONS IN AN ANALOG NEURAL MEMORY
App. No. 17/190,376
→
Method Of Making Memory Cells, High Voltage Devices And Logic Devices On A Substrate With Silicide On Conductive Blocks
App. No. 17/185,709
→
PRECISE DATA TUNING METHOD AND APPARATUS FOR ANALOG NEURAL MEMORY IN AN ARTIFICIAL NEURAL NETWORK
App. No. 17/185,725
→
OUTPUT CIRCUITS FOR AN ANALOG NEURAL MEMORY SYSTEM FOR DEEP LEARNING NEURAL NETWORK
App. No. 17/181,656
→
Method Of Forming Split Gate Memory Cells With Thinner Tunnel Oxide
App. No. 17/179,057
→
VIRTUAL GROUND NON-VOLATILE MEMORY ARRAY
App. No. 17/178,520
→
BASE ASSEMBLIES HAVING CONDUCTIVE PADS FOR KNOB ON DISPLAY DEVICES AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 17/174,963
→
BURN-IN BOARD INCLUDING STRIP SOCKET WITH INTEGRATED HEATING FOR HIGH VOLUME BURN-IN OF SEMICONDUCTOR DEVICES
App. No. 17/174,392
→
THIN-FILM RESISTOR (TFR) WITH IMPROVED CONTACTS
App. No. 17/170,975
→
INTERFACING A NUMBER OF SERIAL COMMUNICATION INTERFACES WITH A PARALLEL COMMUNICATION INTERFACE, AND RELATED SYSTEMS, METHODS, AND APPARATUSES
App. No. 17/171,697
→
METHOD, SYSTEM AND APPARATUS FOR SUPPRESSING CONTROLLER AREA NETWORK BUS RINGING
App. No. 17/164,934
→
SPLIT-GATE NON-VOLATILE MEMORY CELLS WITH ERASE GATES DISPOSED OVER WORD LINE GATES, AND METHOD OF MAKING SAME
App. No. 17/165,934
→
INTEGRATED CIRCUIT BOND PAD WITH MULTI-MATERIAL TOOTHED STRUCTURE
App. No. 17/163,645
→
HEADS-UP DISPLAY USING ELECTROCHROMIC ELEMENTS
App. No. 17/160,958
→
THREE-DIMENSIONAL METAL-INSULATOR-METAL (MIM) CAPACITOR
App. No. 17/155,431
→
METHOD OF FORMING A DEVICE WITH PLANAR SPLIT GATE NON-VOLATILE MEMORY CELLS, HIGH VOLTAGE DEVICES AND FINFET LOGIC DEVICES
App. No. 17/151,944
→
SPLIT GATE NON-VOLATILE MEMORY CELLS, HV AND LOGIC DEVICES WITH FINFET STRUCTURES, AND METHOD OF MAKING SAME
App. No. 17/152,441
→
SPLIT-GATE, 2-BIT NON-VOLATILE MEMORY CELL WITH ERASE GATE DISPOSED OVER WORD LINE GATE, AND METHOD OF MAKING SAME
App. No. 17/152,696
→
SYSTEM AND METHOD FOR SCHEDULING SHARABLE PCIE ENDPOINT DEVICES
App. No. 17/151,316
→
Partitionable Neural Network for Solid State Drives
App. No. 17/148,200
→
SYSTEMS AND METHODS FOR DETECTING FORCER MISALIGNMENT IN A WAFER PROBER
App. No. 17/147,778
→
REDUNDANT ANGULAR POSITION SENSOR AND ASSOCIATED METHOD OF USE
App. No. 17/146,875
→
METHOD, SYSTEM AND APPARATUS FOR CONSTANT, HIGH SWITCHING FREQUENCY AND NARROW DUTY RATIO PWM CONTROL OF DC-DC CONVERTERS AND ACCURATE PFM CONTROL AT LIGHT LOAD
App. No. 17/145,944
→
ADAPTIVE BIAS DECODER TO PROVIDE A VOLTAGE TO A CONTROL GATE LINE IN AN ANALOG NEURAL MEMORY ARRAY IN ARTIFICIAL NEURAL NETWORK
App. No. 17/140,924
→
METHOD FOR ERASING A ReRAM MEMORY CELL
App. No. 17/140,064
→
SENSORS, AUTONOMOUS SENSORS AND RELATED SYSTEMS, METHODS AND DEVICES
App. No. 17/247,954
→
ELECTRICAL ENERGY LOSS DETECTION
App. No. 17/247,837
→
Transparently Attached Flash Memory Security
App. No. 17/133,115
→
INPUT AND DIGITAL OUTPUT MECHANISMS FOR ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
App. No. 17/133,395
→
Method for forming hermetic package for a power semiconductor
App. No. 17/129,144
→
Method Of Making Memory Cells, High Voltage Devices And Logic Devices On A Substrate
App. No. 17/129,865
→
VERIFYING OR READING A CELL IN AN ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
App. No. 17/125,459
→
INPUT AND DIGITAL OUTPUT MECHANISMS FOR ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
App. No. 17/121,555
→
INTEGRATED INDUCTOR WITH A STACKED METAL WIRE
App. No. 17/117,288
→
BACKSIDE INTERCONNECT FOR INTEGRATED CIRCUIT PACKAGE INTERPOSER
App. No. 17/111,973
→
Machine Learning Based Methods and Apparatus for Integrated Circuit Design Delay Calculation and Verification
App. No. 17/111,218
→
METHOD AND SYSTEM FOR ENHANCED SPI COMMUNICATION
App. No. 17/109,315
→
FRONT-END CIRCUITRY FOR A DATA RECEIVER AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 17/247,148
→
WORD LINE AND CONTROL GATE LINE TANDEM DECODER FOR ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK
App. No. 17/104,385
→
METHOD AND APPARATUS FOR PHASE CURRENT BALANCING IN A MULTI-PHASE DC-TO-DC CONVERTER
App. No. 17/101,498
→
SELF-TIMED SENSING ARCHITECTURE FOR A NON-VOLATILE MEMORY SYSTEM
App. No. 17/095,331
→
TEMPERATURE COMPENSATION IN AN ANALOG MEMORY ARRAY BY CHANGING A THRESHOLD VOLTAGE OF A SELECTED MEMORY CELL IN THE ARRAY
App. No. 17/095,661
→
ANALOG NEURAL MEMORY ARRAY IN ARTIFICIAL NEURAL NETWORK WITH SOURCE LINE PULLDOWN MECHANISM
App. No. 17/090,481
→
Regression Neural Network for Identifying Threshold Voltages to be Used in Reads of Flash Memory Devices
App. No. 17/089,891
→
OBFUSCATING CRYPTOGRAPHIC PARAMETERS USED IN ELLIPTICAL CURVE CRYPTOGRAPHY, AND RELATED SYSTEMS AND DEVICES
App. No. 17/086,007
→
ANALOG NEURAL MEMORY ARRAY IN ARTIFICIAL NEURAL NETWORK COMPRISING LOGICAL CELLS AND IMPROVED PROGRAMMING MECHANISM
App. No. 17/082,956
→
INTEGRATED CIRCUIT (IC) PACKAGE WITH INTEGRATED INDUCTOR HAVING CORE MAGNETIC FIELD (B FIELD) EXTENDING PARALLEL TO SUBSTRATE
App. No. 17/074,848
→
OVENS FOR ATOMIC CLOCKS AND RELATED METHODS
App. No. 16/949,222
→
CHARGE PUMP FOR USE IN NON-VOLATILE FLASH MEMORY DEVICES
App. No. 17/075,691
→
SYSTEM AND METHOD FOR AUTO-RECOVERY IN LOCKSTEP PROCESSORS
App. No. 17/075,493
→
SYSTEM AND METHOD FOR MONITORING ANALOG FRONT-END (AFE) CIRCUITRY OF AN INDUCTIVE POSITION SENSOR
App. No. 17/075,157
→
TOUCH SENSOR SIGNAL INTEGRATION
App. No. 16/949,218
→
NON-VOLATILE MEMORY SYSTEM USING STRAP CELLS IN SOURCE LINE PULL DOWN CIRCUITS
App. No. 17/074,103
→
THIN FILM RESISTOR (TFR) FORMED IN AN INTEGRATED CIRCUIT DEVICE USING AN OXIDE CAP LAYER AS A TFR ETCH HARDMASK
App. No. 17/071,584
→
THIN FILM RESISTOR (TFR) FORMED IN AN INTEGRATED CIRCUIT DEVICE USING WET ETCHING OF A DIELECTRIC CAP
App. No. 17/071,356
→
THIN FILM RESISTOR (TFR) FORMED IN AN INTEGRATED CIRCUIT DEVICE USING TFR CAP LAYER(S) AS AN ETCH STOP AND/OR HARDMASK
App. No. 17/071,442
→
Microcontroller with Increasing Protected Storage Area and Erase Protection
App. No. 63/091,333
→
FINFET SPLIT GATE NON-VOLATILE MEMORY CELLS WITH ENHANCED FLOATING GATE TO FLOATING GATE CAPACITIVE COUPLING
App. No. 17/069,563
→
FOREIGN OBJECT DETECTION IN WIRELESS CHARGING SYSTEMS AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 16/949,003
→
NEAR CONSTANT DELAY COMPARATOR FOR CLOSED-LOOP SYSTEM
App. No. 17/065,920
→
SYNCHRONIZATION OF SEQUENCE NUMBERS IN A NETWORK
App. No. 16/948,908
→
MOTOR-CURRENT CONTROL PROCESS FOR PERMANENT-MAGNET SYNCHRONOUS MOTORS AND RELATED SYSTEMS, METHODS AND DEVICES
App. No. 16/948,906
→
LOW COST POWER LINE MODEM
App. No. 17/037,919
→
EtherCAT Controllers
App. No. 17/030,439
→
LOW COST CRYPTOGRAPHIC ACCELERATOR
App. No. 16/948,480
→
PRECISION TUNING OF A PAGE OR WORD OF NON-VOLATILE MEMORY CELLS AND ASSOCIATED HIGH VOLTAGE CIRCUITS FOR AN ANALOG NEURAL MEMORY ARRAY IN AN ARTIFICIAL NEURAL NETWORK
App. No. 17/024,410
→
SYSTEM AND METHOD FOR DATA SAMPLER DRIFT COMPENSATION
App. No. 17/022,480
→
METHOD OF FORMING A THREE-GATE NON-VOLATILE FLASH MEMORY CELL USING TWO POLYSILICON DEPOSITION STEPS
App. No. 17/021,678
→
SYSTEMS AND METHODS FOR IMPROVED ROOT MEAN SQUARE (RMS) MEASUREMENT
App. No. 17/019,514
→
Integrated Circuit (IC) Device Including A Force Mitigation System For Reducing Under-Pad Damage Caused By Wire Bond
App. No. 17/019,768
→
TECHNIQUES FOR ROUTING SIGNALS USING INACTIVE SENSOR REGIONS OF TOUCH SENSORS AND RELATED SYSTEMS AND DEVICES
App. No. 16/948,270
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PULSE-WIDTH MODULATION AND ARBITRATION FOR CONTEXTUAL AND UNIFORM LED ILLUMINATION IN USB APPLICATIONS
App. No. 17/013,978
→