Patent Assignment
Reel/Frame 058263/0292
Assignment of Assignor's Interest
Recorded: 2021-10-07
Pages: 10
Assignors
KSHEERASAGAR, THARUN KUMAR
Executed: 2021-10-07
BHADANA, ROHIT
Executed: 2021-10-07
KASHYAP, HEMANT
Executed: 2021-10-07
RANJAN, PRATYUSH
Executed: 2021-10-07
Assignee
XILINX, INC.
2100 LOGIC DRIVE, SAN JOSE, CALIFORNIA, 95124
Covered Property
(1)
Circuit Design Simulation and Clock Event Reduction