IP Library › Assignment 059411/0196
Patent Assignment
Reel/Frame 059411/0196

Release of Security Interest

Recorded: 2022-03-16 Pages: 80
Assignor
MUFG UNION BANK, N.A.
Executed: 2020-04-16
Assignees
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT, SAN JOSE, CALIFORNIA, 95134
SPANSION LLC
198 CHAMPION COURT, SAN JOSE, CALIFORNIA, 95134
Covered Properties (132)
A System and Method for Erase Voltage Control During Multiple Sector of a Flash Memory Device
Low Power Charge Pump
Erase Algorithm for Multi-Level Bit Flash Memory
Method of Forming Narrowly Spaced Flash Memory Contact Openings and Lithography Masks
Non-Volatile Memory and Sram Based on Resonant Tunneling Devices
Polymer-Based Transistor Devices, Methods, and Systems
Write-Read-Many Times Memory
A Non-Critical Complementary Masking Method for Poly-1 Definition in Flash Memory Device Fabrication
Multi-Chip Module and Method of Manufacture
Memory Cell System with Charge Trap
Integrated Circuit Memory System Employing Silicon Rich Layers
Multiple Communication Channels on Mmc or Sd Cmd Line
Multiple Stakeholder Secure Memory Partitioning and Access Control
Barrier Region for Memory Devices
Resistance Changing Memory Cell Architecture
Die Attachment, Die Stacking, and Wire Embedding Using Film
Oro and Orpro with Bit Line Trench to Suppress Transport Program Disturb
Process of Forming an Electronic Device Including Depositing Layers Within Openings
Semiconductor Device and Method for Manufacturing Thereof
Secure Modular Exponentiation by Randomization of Exponent Scanning
Semiconductor Device and Method for Manufacturing Thereof
Selective Silicide Formation Using Resist Etch Back
Extending Flash Memory Data Retension via Rewrite Refresh
Controlling Ac Disturbance While Programming
Method for Protecting Data Against Differential Fault Analysis Involved in Rivest, Shamir, and Adleman Cryptography Using the Chinese Remainder Theorem
Non-Volatile Memory Device and Methods of Using
Memory Devices and Methods for High Random Transaction Rate
Acoustic Processing Unit
Acoustic Processing Unit Interface
Arithmetic Logic Unit Architecture
Re-Enumeration of Usb 3.0 Compatible Devices
Adaptively Progrmaming or Erasing Flash Memory Blocks
Soft Error Resistant Circuitry
Method, Apparatus, and Manufacture for Flash Memory Adaptive Algorithm
Apparatus and Method for Rounded Ono Formation in a Flash Memory Device
Leakage Reducing Writeline Charge Protection Circuit
Power Savings Apparatus and Method for Memory Device Using Delay Locked Loop
Field-Line Repeater (Flr) Structure of a Sense Array
Capacitance Sensing Devices and Methods
Supply Power Dependent Controllable Write Throughput for Memory Applications
Improved Spacer Design to Prevent Trapped Electrons
Wear Leveling in Flash Memory Devices with Trim Commands
Senone Scoring for Multiple Input Streams
Distribution of Gas Over a Semiconductor Wafer in Batch Processing
Method and System for Processing a Wafer
Inter-Layer Insulator for Electronic Devices and Apparatus for Forming Same
User Interface with Child-Lock Feature
Data Refresh in Non-Volatile Memory
Forming a Substantially Uniform Wing Height Among Elements in a Charge Trap Semicondctor Device
Forming Charge Trap Separation in a Flash Memory Semiconductor Device
Integrated Circuits with Non-Volatile Memory and Methods for Manufacture
Memory First Process Flow and Device
Charge Trapping Device with Improved Select Gate to Memory Gate Isolaton
Use Disposable Gate Cap to Form Transistors, and Split Gate Charge Trapping Memory Cells
Three Dimensional Capacitor
Histogram Based Pre-Pruning Scheme for Active Hmms
Hybrid Hashing Scheme for Active Hmms
Memory Device with Internal Data Processing Logic
Phoneme Score Accelerator
Design for Test (Dft) Read Speed Through Transition Detector in Built-in Self-Test (Bist) Sort
Multi-Chip Package Assembly with Improved Bond Wire Separation
Buried Hard Mask for Embedded Semicon-Ductor Device Patterning
Programmable and Flexible Reference Cell Selection Method for Memory Devices
Distributed Speech Recognition System
Non-Volatile Memory Based System Ram
Pipelining in a Memory
Erase Verification
Authentication for Recognition Systems
Combining of Results from Multiple Decoders
Modified Local Segmented Self-Boosting of Memory Cell Channels
Die Seal Layout for Dual Damascene in a Semiconductor Device
Zero Power Metering Circuits, Systems and Methods
Screening for Reference Cells in a Memory
Methods of Fabricating an F-Ram
Detect and Differentiate Touches from Different Size Conductive Objects on a Capacitive Button
Method of Fabricating a Ferroelectric Capacitor
Eliminating Shorting Between Ferroelectric Capacitors and Metal Contacts During Ferroelectric Random Access Memory Fabrication
Multi-Channel, Multi-Bank Memory with Wide Data Input/Output
Systems, Methods, and Devices for Frequency Calibration of Transmitters
Gate Formation Memory by Planarization
An Esd Clamp with a Layout-Alterable Trigger Voltage and a Holding Voltage Above the Supply Voltage
Programmable Switched Capacitor Block
Booting an Application from Multiple Memories
Encryption Method for Execute-in-Place Memories
Providing a Baseline Capacitance for a Capacitance Sensing Channel
Single Layer Sensor Pattern
Configurable Capacitor Arrays and Switched Capacitor Circuits
Split-Gate Semiconductor Device with L-Shaped Gate
Integrated Circuit Device with Programmable Analog Subsystem
Low Power Capacitive Sensor Button
Capacitive Fingerprint Sensor with Quadrature Demodulator and Multiphase Scanning
Methods and Sensors for Multiphase Scanning in the Fingerprint and Touch Applications
Background Light Detection for Optical Navigation Systems
Overlaid Erase Block Mapping
10T Non Volatile Static Random-Access Memory
Programmable Switched Capacitor Block
Full-Wave Synchronous Rectification for Self-Capacitance Sensing
Integrated Circuit Device with Programmable Analog Subsystem
Systems, Methods, and Devices for Touch Event and Hover Event Detection
Low-Power Touch Button Sensing System
Control Circuit
Non-Volatile Static Ram and Method of Operation Thereof
Phase Controller Apparatus and Methods
Low Thermal Design for Dc-Dc Converter
On-Vehicle Electronic Device
A Low-Power Type-C Receiver with High Idle Noise and Dc-Level Rejection
Analog to Digital Converter
Switching Circuit
A Low-Power Implementation of Type-C Connector Subsystem
Protecting Circuit and Integrated Circuit
Delta Modulator Receive Channel for Capacitance Measurement Circuits
Multiphase Fingerprint Sensor Layout and Construction
Vertical Division of Three-Dimensional Memory Device
Baseline Compensation for Capacitive Sensing
Method for Fabricating Ferroelectric Random-Access Memory on Pre-Patterned Bottom Electrode and Oxidation Barrier
Tape Chip on Lead Using Paste Die Attach Material
Differential Sigma-Delta Capacitance Sensing Devices and Methods
Half-Bridge Fingerprint Sensing Method
Fingerprint Sensor Pattern
An Integrated Circuit to Convert No-Wire Signals to One-Wire Signals
Multi-Bit Non-Volatile Random-Access Memory Cells
Hydrogen Barriers in a Copper Interconnect Process
Hybrid Reference Generation for Ferroelectric Random Access Memory
Fingerprint Sensor-Compatiable Overlay Material
Fingerprint Sensor-Compatible Overlay
Quasi-Differential Mutual Capacitance Measurement
Methods and Devices for Reducing Program Disturb in Non-Volatile Memory Cell Arrays
Configurable and Power-Optimized Integrated Gate-Driver for Usb Power-Delivery and Type-C Socs
Adjustable Over-Current Detector Circuit for Universal Serial Bus (Usb) Devices
Methods and Devices for Reading Data from Non-Volatile Memory Cells
Transceiver for Communication and Method for Controlling Communication
Ratio-Metric Self-Capacitance-to-Code Convertor
Related Assignments (3)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Nov 15, 2007
From: ADVANCED MICRO DEVICES, INC.
To: SPANSION INC.
Reel/Frame 020120/0592 →
Assignment of Assignor's Interest Nov 15, 2007
From: SPANSION INC.
To: SPANSION LLC
Reel/Frame 020120/0718 →
Patent Security Agreement Apr 25, 2017
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 042326/0396 →