Patent Assignment
Reel/Frame 059896/0869
Assignment of Assignor's Interest
Recorded: 2022-05-13
Pages: 3
Assignors
J, RAJA PRABHU
Executed: 2022-05-11
SASI, SANDEEP
Executed: 2022-05-11
REDDY, HARSHAVARDHAN
Executed: 2022-05-11
Assignee
SHAOXING YUANFANG SEMICONDUCTOR CO., LTD.
ROOM 203, 204 AND 206, 2ND FLOOR, BUILDING 3, NO.326 YINQIAO ROAD,GAOBU STREET,YUECHENG DISTRICT, SHAOXIN, ZJ, CHINA
Covered Property
(1)
Reduction of Noise in Output Clock Due to Unequal Successive Time Periods of a Reference Clock in a Fractional-N Phase Locked Loop
Related Assignments
(1)
Other recorded transfers of the patent in this record — the chain of ownership.