Patent Assignment
Reel/Frame 061225/0810
Assignment of Assignor's Interest
Recorded: 2022-09-27
Pages: 9
Assignors
FOUTZ, BRIAN
Executed: 2022-09-19
CHICKERMANE, VIVEK
Executed: 2022-09-20
NANDAKUMAR, BHARATH
Executed: 2022-09-19
CHILLARIGE, SAMEER CHAKRAVARTHY
Executed: 2022-09-19
CHAKRAVADHANULA, KRISHNA
Executed: 2022-09-19
RAI, PRATEEK KUMAR
Executed: 2022-09-19
Assignee
CADENCE DESIGN SYSTEMS, INC.
2655 SEELY AVENUE, SAN JOSE, CALIFORNIA, 95134
Covered Property
(1)
Clock-Based Test-Point Flop Sharing in a Circuit Design
Patent:
12,475,288 →
Application:
17/953,693 →