IP Library Assignment 062162/0137
Patent Assignment
Reel/Frame 062162/0137

Assignment of Assignor's Interest

Recorded: 2022-12-20 Pages: 5
Assignors
KOKKALA, CHRYSA
Executed: 2022-11-24
MITAS, NIKOLAOS
Executed: 2022-11-23
STAMOULIS, IAKOVOS
Executed: 2022-11-24
KERAMIDAS, GEORGIOS
Executed: 2022-11-23
Assignee
THINK SILICON RESEARCH AND TECHNOLOGY SINGLE MEMBER S.A.
PATRAS SCIENCE PARK, RION ACHAIAS, 26504, GREECE
Covered Property (1)
System and Method for Memory Bandwidth Reduction Using a Programmable Cache Line
Application: 18/068,938 →
Publication: US 2025/0291721
Related Assignments (2)
Other recorded transfers of the patent in this record — the chain of ownership.
Change of Name Mar 6, 2026
From: THINK SILICON RESEARCH AND TECHNOLOGY SINGLE MEMBER S.A.
To: THINK SILICON SINGLE MEMBER P.C.
Reel/Frame 075032/0035 →
Assignment of Assignor's Interest Jun 9, 2026
From: THINK SILICON SINGLE MEMBER P.C. AND APPLIED MATERIALS, INC.
To: QUALCOMM INCORPORATED
Reel/Frame 075735/0803 →