Patent Assignment
Reel/Frame 064803/0368
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF ASSIGNEE'S NAME FROM "STATS CHIPPAC PTE. LTE." TO "STATS CHIPPAC PTE. LTD." PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0227. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT.
Recorded: 2023-09-01
Received: 2023-09-01
Pages: 19
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTD.
5 YISHUN STREET 23, SINGAPORE, SXX, SINT MAARTEEN
Covered Applications
(62)
DEVICES, SYSTEMS AND METHODS FOR PRENATAL SEX (GENDER) TESTING
App. No. 62/609,086
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE WITH CONDUCTIVE PADS HAVING EXPANDED INTERCONNECT SURFACE AREA FOR ENHANCED INTERCONNECTION PROPERTIES
App. No. 13/768,862
→
Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD)
App. No. 13/765,478
→
SOLDER JOINT FLIP CHIP INTERCONNECTION HAVING RELIEF STRUCTURE
App. No. 13/756,817
→
Semiconductor Device and Method of Forming Conductive TSV With Insulating Annular Ring
App. No. 13/691,578
→
STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 13/649,834
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND UNDERFILL AND METHOD OF MANUFACTURE THEREOF
App. No. 13/597,086
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ARRAY CONTACTS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/586,178
→
Semiconductor Device and Method of Forming Discontinuous ESD Protection Layers Between Semiconductor Die
App. No. 13/560,008
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WAFERSCALE SPACER
App. No. 13/536,268
→
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING WARPAGE PREVENTION STRUCTURES
App. No. 13/526,877
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THROUGH SILICON VIA AND METHOD OF MANUFACTURE THEREOF
App. No. 13/517,897
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
App. No. 13/495,663
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE PREVENTING MECHANISM AND METHOD OF MANUFACTURE THEREOF
App. No. 13/490,908
→
EMBEDDED SEMICONDUCTOR DIE PACKAGE AND METHOD OF MAKING THE SAME USING METAL FRAME CARRIER
App. No. 13/446,741
→
ELECTRONIC SYSTEM WITH EXPANSION FEATURE
App. No. 13/441,550
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ULTRA-THIN CHIP AND METHOD OF MANUFACTURE THEREOF
App. No. 13/426,529
→
SEMICONDUCTOR DEVICE AND METHOD OF SHIELDING SEMICONDUCTOR DIE FROM INTER-DEVICE INTERFERENCE
App. No. 13/339,185
→
Semiconductor Package Having Semiconductor Die with Internal Vertical Interconnect Structure and Method Therefor
App. No. 13/335,867
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/327,529
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SLUG AND METHOD OF MANUFACTURE THEREOF
App. No. 13/325,359
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH COUPLING FEATURES AND METHOD OF MANUFACTURE THEREOF
App. No. 13/326,116
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING FO-WLCSP WITH MULTIPLE ENCAPSULANTS
App. No. 13/326,157
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT CONDUCTION AND METHOD OF MANUFACTURE THEREOF
App. No. 13/325,530
→
SEMICONDUCTOR DEVICE HAVING AN INTERCONNECT STRUCTURE WITH TSV USING ENCAPSULANT FOR STRUCTURAL SUPPORT
App. No. 13/245,099
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXTERNAL WIRE CONNECTION AND METHOD OF MANUFACTURE THEREOF
App. No. 13/244,262
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
App. No. 13/243,886
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACK DEVICE
App. No. 13/243,699
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND METHOD OF MANUFACTURE THEREOF
App. No. 13/237,918
→
SEMICONDUCTOR DEVICE AND METHOD OF SELF-CONFINEMENT OF CONDUCTIVE BUMP MATERIAL DURING REFLOW WITHOUT SOLDER MASK
App. No. 13/218,653
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DIE PADDLE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/197,070
→
LEADLESS INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
App. No. 13/195,465
→
SEMICONDUCTOR PACKAGE AND METHOD OF MOUNTING SEMICONDUCTOR DIE TO OPPOSITE SIDES OF TSV SUBSTRATE
App. No. 13/191,386
→
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING A CAVITY
App. No. 13/187,252
→
FLIP CHIP INTERCONNECTION STRUCTURE
App. No. 13/175,694
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/166,802
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THERMAL DISPERSAL STRUCTURES AND METHOD OF MANUFACTURE THEREOF
App. No. 13/163,611
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FORMED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/102,052
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PLATED LEADS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/069,744
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/966,071
→
Semiconductor Device and Method of Confining Conductive Bump Material with Solder Mask Patch
App. No. 12/963,919
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF
App. No. 12/961,489
→
Ultra Thin Bumped Wafer With Under-Film
App. No. 12/911,592
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERLOCK AND METHOD OF MANUFACTURE THEREOF
App. No. 12/890,491
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
App. No. 12/730,989
→
Extended Redistribution Layers Bumped Wafer
App. No. 12/704,345
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A STACKABLE PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/639,990
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A LEADED PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/565,144
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTEGRAL-INTERPOSER-STRUCTURE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/410,945
→
INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM AND METHOD OF MANUFACTURE THEREOF
App. No. 12/371,730
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INPUT/OUTPUT EXPANSION
App. No. 12/333,298
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED PADDLE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/328,759
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ANTI-PEEL CONTACT PADS
App. No. 12/235,288
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERPOSER
App. No. 12/040,558
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SYSTEM AND APPARATUS FOR WAFER LEVEL INTEGRATION OF COMPONENTS
App. No. 11/965,383
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INTEGRATED CIRCUIT PACKAGE SYSTEM HAVING PERIMETER PADDLE
App. No. 11/766,771
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACK
App. No. 11/762,055
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ELECTRONIC SYSTEM WITH VERTICAL INTERMETALLIC COMPOUND
App. No. 11/758,635
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH BONDING LANDS
App. No. 11/677,477
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INTEGRATED PASSIVE DEVICE SYSTEM
App. No. 11/553,949
→
Integrated circuit package system with exposed interconnects
App. No. 11/354,806
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INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING WIDE FLANGE LEADFRAME
App. No. 11/307,129
→