Patent Assignment
Reel/Frame 065334/0488
RELEASE OF SECURITY INTEREST
Recorded: 2023-10-25
Received: 2023-10-25
Pages: 22
Assignor
NXP B.V.
Executed: 2023-10-24
Assignee
CROCUS TECHNOLOGY INC.
870 N MCCARTHY BLVD., SUITE 220, MILPITAS, CA, 95305, UNITED STATES
Covered Applications
(29)
THERMALLY STABLE REFERENCE VOLTAGE GENERATOR FOR MRAM
App. No. 12/765,897
→
METHOD AND DEVICE FOR PROTECTION OF AN MRAM DEVICE AGAINST TAMPERING
App. No. 12/708,874
→
ACTIVE SHIELDING FOR A CIRCUIT COMPRISING MAGNETICALLY SENSITIVE MATERIALS
App. No. 12/277,537
→
NANOWIRE MAGNETIC RANDOM ACCESS MEMORY
App. No. 12/088,724
→
TAMPER-RESISTANT PACKAGING AND APPROACH USING MAGNETICALLY-SET DATA
App. No. 10/541,884
→
THERMALLY STABLE REFERENCE VOLTAGE GENERATOR FOR MRAM
App. No. 11/547,336
→
METHOD AND DEVICE FOR PERFORMING ACTIVE FIELD COMPENSATION DURING PROGRAMMING OF A MAGNETORESISTIVE MEMORY DEVICE
App. No. 10/579,933
→
NON-HOMOGENEOUS SHIELDING OF AN MRAM CHIP WITH MAGNETIC FIELD SENSOR
App. No. 10/579,929
→
DATA RETENTION INDICATOR FOR MAGNETIC MEMORIES
App. No. 10/579,934
→
METHOD AND DEVICE FOR PREVENTING ERRONEOUS PROGRAMMING OF A MAGNETORESISTIVE MEMORY ELEMENT
App. No. 10/579,935
→
MAGNETIC FIELD SHAPING CONDUCTOR
App. No. 10/574,365
→
ACTIVE SHIELDING FOR A CIRCUIT COMPRISING MAGNETICALLY SENSITIVE MATERIALS
App. No. 10/570,174
→
COMPENSATING A LONG READ TIME OF A MEMORY DEVICE IN DATA COMPARISON AND WRITE OPERATIONS
App. No. 10/565,149
→
INTEGRITY CONTROL FOR DATA STORED IN A NON-VOLATILE MEMORY
App. No. 10/559,174
→
SIMULTANEOUS READING FROM AND WRITING TO DIFFERENT MEMORY CELLS
App. No. 10/549,559
→
MRAM ARCHITECTURE FOR LOW POWER CONSUMPTION AND HIGH SELECTIVITY
App. No. 10/543,396
→
MEMORY CONTROLLER AND METHOD FOR WRITING TO A MEMORY
App. No. 10/541,266
→
HARDWARE SECURITY DEVICE FOR MAGNETIC MEMORY CELLS
App. No. 10/539,795
→
METHOD AND DEVICE FOR PROTECTION OF AN MRAM DEVICE AGAINST TAMPERING
App. No. 10/539,548
→
Tamper-resistant packaging and approach
App. No. 10/538,457
→
TAMPER RESISTANT PACKAGING AND APPROACH
App. No. 10/538,454
→
MAGNETIC MEMORY ARCHITECTURE WITH SHARED CURRENT LINE
App. No. 10/536,292
→
METHOD AND DEVICE TO DETECT THE LIKELY ONSET OF THERMAL RELAXATION IN MAGNETIC DATA STORAGE DEVICES
App. No. 10/536,291
→
METHOD AND DEVICE FOR IMPROVED MAGNETIC FIELD GENERATION DURING A WRITE OPERATION OF A MAGNETORESISTIVE MEMORY DEVICE
App. No. 10/536,293
→
CURRENT RE-ROUTING SCHEME FOR SERIAL-PROGRAMMED MRAM
App. No. 10/536,271
→
Method and device for persistent-memory mangement
App. No. 10/533,735
→
MRAM-CELL AND ARRAY-ARCHITECTURE WITH MAXIMUM READ-OUT SIGNAL AND REDUCED ELECTROMAGNETIC INTERFERENCE
App. No. 10/515,475
→
MAGNETORESISTIVE MEMORY CELL ARRAY AND MRAM MEMORY COMPRISING SUCH ARRAY
App. No. 10/515,155
→
MEMORY HAVING PLURAL MAGNETIC LAYERS AND A SHIELDING LAYER
App. No. 09/886,184
→