Patent Assignment
Reel/Frame 069168/0273
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2024-10-11
Received: 2024-10-11
Pages: 43
Assignor
SANDISK TECHNOLOGIES, INC.
Executed: 2024-10-08
Assignee
WESTERN DIGITAL TECHNOLOGIES, INC.
5601 GREAT OAKS PARKWAY, LEGAL DEP., SAN JOSE, CA, 95119, UNITED STATES
Covered Applications
(100)
SAFETY MECHANISM FOR AN ADJUSTABLE DUMBBELL
App. No. 18/537,480
→
LEADERBOARD WITH IRREGULARITY FLAGS IN AN EXERCISE MACHINE SYSTEM
App. No. 18/242,840
→
Generalized Verification Scheme For Safe Metadata Modification
App. No. 17/744,551
→
Method and System for Decoding Data based on Association of First Memory Location and Second Memory Location
App. No. 17/503,198
→
Systems and Methods for Allocating Blocks of Memory to Multiple Zones Associated with Corresponding Error Correction Mechanisms
App. No. 17/501,890
→
FABRIC INTERCONNECTION FOR MEMORY BANKS BASED ON NETWORK-ON-CHIP METHODOLOGY
App. No. 17/486,528
→
Methods and Systems for Implementing Redundancy in Memory Controllers
App. No. 17/463,340
→
Address Translation for Storage Device
App. No. 17/357,852
→
Methods and Systems for Object Level De-Duplication for Data Storage System
App. No. 17/315,202
→
Data Storage System and Method for Multiple Communication Protocols and Memory Access
App. No. 17/244,799
→
Operating Parameters for Non-Volatile Memory Devices
App. No. 17/177,102
→
MATRIX-VECTOR MULTIPLICATION USING SOT-BASED NON-VOLATILE MEMORY CELLS
App. No. 17/172,155
→
SOT-BASED SPIN TORQUE OSCILLATORS FOR OSCILLATORY NEURAL NETWORKS
App. No. 17/172,175
→
System Data Storage Mechanism Providing Coherency and Segmented Data Loading
App. No. 17/153,719
→
INVALIDATION DATA AREA FOR CACHE
App. No. 17/068,700
→
INTELLIGENT WIDE PORT PHY USAGE
App. No. 16/928,954
→
Data Storage System and Method for Multiple Communication Protocols and Direct Memory Access
App. No. 16/911,312
→
Data Storage Device, Method and System, and Control of Data Storage Device Based on Writing Operations and Lifetime
App. No. 16/827,597
→
Wear Leveling in Solid State Devices
App. No. 16/827,605
→
Systems and Methods for Multi-Zone Data Tiering for Endurance Extension in Solid State Drives
App. No. 16/824,508
→
Soft-Decision Input Generation for Data Storage Systems
App. No. 16/823,235
→
Methods and Systems for Implementing Redundancy in Memory Controllers
App. No. 16/818,949
→
Calibrating Optimal Read Levels
App. No. 16/752,516
→
MULTI-TIER SCHEME FOR LOGICAL STORAGE MANAGEMENT
App. No. 16/751,124
→
SYSTEM AND METHOD FOR COPY ON WRITE ON AN SSD
App. No. 16/746,663
→
Data Storage System and Method for Decoding Data based on Extrapolated Flipped-Bit Data
App. No. 16/716,378
→
SYSTEM AND METHOD FOR DIRECT MEMORY ACCESS IN A FLASH STORAGE
App. No. 16/554,519
→
System Data Storage Mechanism Providing Coherency and Segmented Data Loading
App. No. 16/523,951
→
Generalized Verification Scheme For Safe Metadata Modification
App. No. 16/523,960
→
WRITE OPERATION VERIFICATION METHOD AND APPARATUS
App. No. 16/455,564
→
SYSTEM AND METHOD FOR DECODING ITERATIONS AND DYNAMIC SCALING
App. No. 16/453,882
→
ADDRESS TRANSLATION FOR STORAGE DEVICE
App. No. 16/452,463
→
MULTI-TIER SCHEME FOR LOGICAL STORAGE MANAGEMENT
App. No. 16/370,811
→
OPERATING PARAMETERS FOR FLASH MEMORY DEVICES
App. No. 16/282,227
→
FLASH STORAGE DEVICE WITH DATA INTEGRITY PROTECTION
App. No. 16/216,904
→
METHODS AND SYSTEMS FOR OBJECT LEVEL DE-DUPLICATION FOR SOLID STATE DEVICES
App. No. 16/191,210
→
METHODS AND SYSTEMS FOR IMPLEMENTING REDUNDANCY IN MEMORY CONTROLLERS
App. No. 16/164,730
→
SYSTEMS AND METHODS FOR OFFLOADING PROCESSING FROM A HOST TO STORAGE PROCESSING UNITS USING AN INTERCONNECT NETWORK
App. No. 16/149,091
→
CHARACTERIZING AND OPERATING A NON-VOLATILE MEMORY DEVICE
App. No. 16/116,806
→
SOFT-DECISION INPUT GENERATION FOR DATA STORAGE SYSTEMS
App. No. 16/112,429
→
DIFFUSED RESISTIVE MEMORY CELL WITH BURIED ACTIVE ZONE
App. No. 16/110,079
→
COLLISION DETECTION FOR SLAVE STORAGE DEVICES
App. No. 16/022,542
→
MULTI-LEVEL PHASE CHANGE DEVICE
App. No. 16/017,806
→
OPTIMIZED GARBAGE COLLECTION FOR SOLID-STATE STORAGE DEVICES
App. No. 16/013,599
→
POWER-SAFE DATA MANAGEMENT SYSTEM
App. No. 16/011,569
→
WEAR LEVELING IN SOLID STATE DEVICES
App. No. 16/011,572
→
Efficiently and Dynamically Sized Reverse Map to Handle Variable Size Data
App. No. 15/995,945
→
SYSTEM AND METHOD FOR DIRECT MEMORY ACCESS IN A FLASH STORAGE
App. No. 15/971,971
→
INTELLIGENT WIDE PORT PHY USAGE
App. No. 15/967,522
→
REDUCING WRITE-BACKS TO MEMORY BY CONTROLLING THE AGE OF CACHE LINES IN LOWER LEVEL CACHE
App. No. 15/958,563
→
SOFT INFORMATION MODULE
App. No. 15/882,937
→
IMPLEMENTING DEPOSITION GROWTH METHOD FOR MAGNETIC MEMORY
App. No. 15/876,632
→
SYSTEM AND METHOD FOR COPY ON WRITE ON AN SSD
App. No. 15/876,245
→
TILTED SYNTHETIC ANTIFERROMAGNET POLARIZER/REFERENCE LAYER FOR STT-MRAM BITS
App. No. 15/844,769
→
Library for Seamless Management of Storage Devices
App. No. 15/828,229
→
THREE TERMINAL SOT MEMORY CELL WITH ANOMALOUS HALL EFFECT
App. No. 15/822,500
→
APPARATUS AND METHOD FOR LOW POWER LOW LATENCY HIGH CAPACITY STORAGE CLASS MEMORY
App. No. 15/716,467
→
TILTED SYNTHETIC ANTIFERROMAGNET POLARIZER/REFERENCE LAYER FOR STT-MRAM BITS
App. No. 15/696,637
→
COMPONENT PLACEMENT WITHIN A SOLID STATE DRIVE
App. No. 15/669,685
→
PLANAR VARIABLE RESISTANCE MEMORY
App. No. 15/667,000
→
WEAR LEVELING IN NON-VOLATILE MEMORIES
App. No. 15/627,135
→
WEAR LEVELING IN NON-VOLATILE MEMORIES
App. No. 15/627,091
→
DETERMINING CONTROL STATES FOR ADDRESS MAPPING IN NON-VOLATILE MEMORIES
App. No. 15/627,042
→
MEMORY UNIT ASSIGNMENT AND SELECTION FOR INTERNAL MEMORY OPERATIONS IN DATA STORAGE SYSTEMS
App. No. 15/495,900
→
APPARATUS WITH A MEMORY CONTROLLER CONFIGURED TO CONTROL ACCESS TO RANDOMLY ACCESSIBLE NON-VOLATILE MEMORY
App. No. 15/489,282
→
ADDRESS TRANSLATION FOR A NON-VOLATILE MEMORY STORAGE DEVICE
App. No. 15/489,632
→
METHODS AND SYSTEMS FOR IMPLEMENTING REDUNDANCY IN MEMORY CONTROLLERS
App. No. 15/484,039
→
CHARACTERIZING AND OPERATING A NON-VOLATILE MEMORY DEVICE
App. No. 15/484,038
→
DATA RETENTION FLAGS IN SOLID-STATE DRIVES
App. No. 15/484,044
→
NANO-IMPRINTED SELF-ALIGNED MULTI-LEVEL PROCESSING METHOD
App. No. 15/477,739
→
APPARATUS AND METHOD FOR INSERTION AND DELETION IN MULTI-DIMENSIONAL TO LINEAR ADDRESS SPACE TRANSLATION
App. No. 15/470,695
→
APPARATUS AND METHOD FOR USING FIELDS IN N-SPACE TRANSLATION OF STORAGE REQUESTS
App. No. 15/458,945
→
VERTICALLY INTEGRATED STORAGE
App. No. 15/452,606
→
ACCESS NETWORK FOR ADDRESS MAPPING IN NON-VOLATILE MEMORIES
App. No. 15/449,612
→
MULTI-TIER SCHEME FOR LOGICAL STORAGE MANAGEMENT
App. No. 15/445,921
→
CALIBRATING OPTIMAL READ LEVELS
App. No. 15/436,697
→
METHOD FOR FORMING PCM AND RRAM 3-D MEMORY CELLS
App. No. 15/412,566
→
MULTI-LEVEL PHASE CHANGE DEVICE
App. No. 15/406,221
→
APPARATUS AND METHOD FOR SINGLE PASS ENTROPY DETECTION ON DATA TRANSFER
App. No. 15/380,826
→
IMPLEMENTING MAGNETIC MEMORY PILLAR DESIGN
App. No. 15/369,601
→
INVALIDATION DATA AREA FOR CACHE
App. No. 15/357,155
→
PROGRAMMABLE INPUT/OUTPUT (PIO) ENGINE INTERFACE ARCHITECTURE WITH DIRECT MEMORY ACCESS (DMA) FOR MULTI-TAGGING SCHEME FOR STORAGE DEVICES
App. No. 15/355,851
→
METHODS, DEVICES AND SYSTEMS FOR SOLID STATE DRIVE CONTROL
App. No. 15/345,100
→
Managing the Write Performance of an Asymmetric Memory System
App. No. 15/332,740
→
METHOD FOR FABRICATING MRAM BITS ON A TIGHT PITCH
App. No. 15/280,094
→
METHODS, DEVICES AND SYSTEMS FOR TWO STAGE POWER-ON MAP REBUILD WITH FREE SPACE ACCOUNTING IN A SOLID STATE DRIVE
App. No. 15/275,670
→
EMBEDDED NON-VOLATILE MEMORY
App. No. 15/236,600
→
MANAGING WEAR OF SYSTEM AREAS OF STORAGE DEVICES
App. No. 15/226,590
→
APPARATUS AND METHOD FOR DETERMINING AN OPERATING CONDITION OF A MEMORY CELL BASED ON CYCLE INFORMATION
App. No. 15/207,414
→
IMPLEMENTING DEPOSITION GROWTH METHOD FOR MAGNETIC MEMORY
App. No. 15/197,847
→
FAST SECURE ERASE IN A FLASH SYSTEM
App. No. 15/181,251
→
POWER-SAFE DATA MANAGEMENT SYSTEM
App. No. 15/174,955
→
SYSTEM AND METHOD FOR DYNAMIC SCALING OF LDPC DECODER IN A SOLID STATE DRIVE
App. No. 15/162,504
→
SYSTEM AND METHOD FOR DIRECT MEMORY ACCESS IN A FLASH STORAGE
App. No. 15/156,267
→
NON-BINARY LDPC DECODER USING BINARY SUBGROUP PROCESSING
App. No. 15/150,340
→
ZONING OF LOGICAL TO PHYSICAL DATA ADDRESS TRANSLATION TABLES WITH PARALLELIZED LOG LIST REPLAY
App. No. 15/147,465
→
GENERALIZED WRITE OPERATIONS VERIFICATION METHOD
App. No. 15/146,685
→
DIFFUSED RESISTIVE MEMORY CELL WITH BURIED ACTIVE ZONE
App. No. 15/145,648
→
RESIDUAL CAPACITANCE PERFORMANCE BOOSTER
App. No. 15/145,575
→
GENERALIZED VERIFICATION SCHEME FOR SAFE METADATA MODIFICATION
App. No. 15/140,241
→