Patent Assignment
Reel/Frame 073762/0305
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2026-02-11
Received: 2026-02-11
Pages: 10
Assignor
GALLAGHER IP SOLUTIONS LLC
Executed: 2026-02-03
Assignee
UNIQUIFY IP HOLDINGS, LLC
2030 FORTUNE DRIVE, SUITE 200, SAN JOSE, CA, 95131, UNITED STATES
Covered Applications
(35)
IMPLEMENTATIONS AND METHODS FOR USING MOBILE DEVICES TO COMMUNICATE WITH A NEURAL NETWORK SEMICONDUCTOR
App. No. 18/726,723
→
IMPLEMENTATIONS AND METHODS FOR PROCESSING NEURAL NETWORK IN SEMICONDUCTOR HARDWARE
App. No. 18/288,153
→
CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS
App. No. 18/209,083
→
DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD
App. No. 18/208,050
→
SYSTEMS AND METHODS INVOLVING ARTIFICIAL INTELLIGENCE AND CLOUD TECHNOLOGY FOR EDGE AND SERVER SOC
PCTPCTUS2022027496
→
SYSTEMS AND METHODS INVOLVING ARTIFICIAL INTELLIGENCE AND CLOUD TECHNOLOGY FOR SERVER SOC
PCTPCTUS2022027242
→
IMPLEMENTATIONS AND METHODS FOR PROCESSING NEURAL NETWORK IN SEMICONDUCTOR HARDWARE
PCTPCTUS2022027035
→
DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD
App. No. 17/728,673
→
CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS
App. No. 17/724,221
→
CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS
App. No. 17/074,403
→
DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD
App. No. 16/909,871
→
DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD
App. No. 16/584,600
→
DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD
App. No. 16/296,025
→
DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD
App. No. 16/049,693
→
DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD
App. No. 15/996,365
→
METHOD FOR CALIBRATING CAPTURING READ DATA IN A READ DATA PATH FOR A DDR MEMORY INTERFACE CIRCUIT
App. No. 15/926,902
→
METHOD FOR CALIBRATING CAPTURING READ DATA IN A READ DATA PATH FOR A DDR MEMORY INTERFACE CIRCUIT
App. No. 15/722,209
→
Multiple Gating Modes and Half-Frequency Dynamic Calibration for DDR Memory Controllers
App. No. 15/249,188
→
CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS
App. No. 15/237,473
→
CIRCUIT FOR DYNAMICALLY ADAPTIVE BIT-LEVELING BY INCREMENTAL SAMPLING, JITTER DETECTION, AND EXCEPTION HANDLING
App. No. 15/078,939
→
Multiple Gating Modes and Half-Frequency Dynamic Calibration for DDR Memory Controllers
App. No. 14/882,226
→
CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS
App. No. 14/850,792
→
METHODS FOR CALIBRATING A READ DATA PATH FOR A MEMORY INTERFACE
App. No. 14/752,903
→
METHODS FOR DYNAMICALLY ADAPTIVE BIT-LEVELING BY INCREMENTAL SAMPLING, JITTER DETECTION, AND EXCEPTION HANDLING
App. No. 14/273,416
→
CONTINUOUS ADAPTIVE TRAINING FOR DATA INTERFACE TIMING CALIBRATION
App. No. 14/205,208
→
METHOD FOR OPERATING A CIRCUIT INCLUDING A TIMING CALIBRATION FUNCTION
App. No. 14/205,254
→
DATA INTERFACE CIRCUIT FOR CAPTURING RECEIVED DATA BITS INCLUDING CONTINUOUS CALIBRATION
App. No. 14/205,239
→
METHOD FOR OPERATING A DATA INTERFACE CIRCUIT WHERE A CALIBRATION CONTROLLER CONTROLS BOTH A MISSION PATH AND A REFERENCE PATH
App. No. 14/205,225
→
Method of Application Memory Preservation for Dynamic Calibration of Memory Interfaces
App. No. 14/152,807
→
Application Memory Preservation for Dynamic Calibration of Memory Interfaces
App. No. 14/152,902
→
MEMORY INTERFACE CIRCUITS INCLUDING CALIBRATION FOR CAS LATENCY COMPENSATION IN A PLURALITY OF BYTE LANES
App. No. 14/081,806
→
METHODS FOR OPERATING A MEMORY INTERFACE CIRCUIT INCLUDING CALIBRATION FOR CAS LATENCY COMPENSATION IN A PLURALITY OF BYTE LANES
App. No. 14/081,897
→
Dynamically Calibrated DDR Memory Controller
App. No. 14/023,630
→
DYNAMICALLY CALIBRATED DDR MEMORY CONTROLLER
App. No. 13/172,740
→
DDR MEMORY CONTROLLER
App. No. 12/157,081
→