Nanowire-based vertical memory cell array having a metal layer interposed between a common back plate and the nanowires
View Patent ↗The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator. At least one bitline extending on a top of the plurality of vertical nanowires and in electrical contact therewith; and at least one wordline formed on vertical sidewalls of the plurality of vertical nanowires and separated therefrom by the dielectric material.
1. A vertical memory cell array, comprising:
a plurality of vertical nanowires extending from an insulator layer;
a dielectric material on vertical sidewalls of the plurality of vertical nanowires;
doped material provided between the plurality of vertical nanowires;
at least one bitline extending on a top of the plurality of vertical nanowires and in electrical contact therewith;
at least one wordline formed on the vertical sidewalls of the plurality of vertical nanowires and separated therefrom by the dielectric material;
a silicide on a top of each of the nanowires and in electrical contact with the at least one bitline; and
a metal layer on the vertical sidewalls of the plurality of vertical nanowires, separating a second dielectric material from contacting the vertical sidewalls of the plurality of vertical nanowires.
2. The vertical memory cell array of claim 1 , wherein the metal layer and the second dielectric material are vertically recessed to below a top surface of the plurality of vertical nanowires such that they are electrically isolated from the silicide.
3. The vertical memory cell array of claim 2 , wherein the dielectric material further comprises a high-k dielectric material formed on exposed portions of the plurality of vertical nanowires and the at least one wordline is formed on the high-k dielectric material.
4. A vertical memory cell, comprising:
a plurality of vertical nanowires;
a high-k dielectric material on vertical sidewalls of the plurality of vertical nanowires;
doped polysilicon material provided between the plurality of vertical nanowires;
at least one metal formed on vertical sidewalls of the plurality of vertical nanowires over the high-k dielectric material and electrically isolated from the doped polysilicon material;
at least one metal extending on a top of the plurality of vertical nanowires, in electrical contact with the plurality of vertical nanowires and electrically isolated from the doped polysilicon material;
a silicide on a top of each of the nanowires and in electrical contact with the at least one metal extending on the top of the plurality of vertical nanowires; and
a metal layer on the vertical sidewalls of the plurality of vertical nanowires, separating the high-k dielectric material from contacting the vertical sidewalls of the plurality of vertical nanowires, wherein the metal layer and the high-k dielectric material are vertically recessed to below a top surface of the plurality of vertical nanowires such that they are electrically isolated from the silicide.
5. The vertical memory cell of claim 4 , further comprising a second high-k dielectric material formed on exposed portions of the plurality of vertical nanowires.