IP Library › Granted Patent US 10,418,982
Granted Patent B2
US 10,418,982 · App. 16/113,235 · Granted Sep 17, 2019

Folded divider architecture

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Quick Facts
Patent No.
US 10,418,982
App. No.
16/113,235
Filed
Aug 27, 2018
Granted
Sep 17, 2019
Kind
B2
Examiner
CHENG, DIANA
Art Unit
2842
USPC
327/115
Abstract

A method includes loading a clock divider counter with most significant bits (MSBs) of a divider value, decrementing the counter at a same edge of each pulse of a clock signal, and comparing a value contained in the counter to a reference value and generating an end count signal if the value contained in the counter matches the reference value. If the value is even, the reference value is set to 1. If the value is odd, the reference value is set to 1, except for every other assertion of the end count signal, where the reference value is instead set to 0. A toggle signal transitions at a same edge of each pulse of the end count signal. The counter is reloaded with MSBs of the divider value based upon the end count signal. A divided version of the clock signal is generated based upon the toggle signal.

Claims (89)

1. A method, comprising:

loading a clock divider counter with most significant bits of a divider value;

decrementing the clock divider counter at a same edge of each pulse of a clock signal;

comparing a value contained in the clock divider counter to a reference value and generating an end count signal as a function of the value contained in the clock divider counter matching the reference value, using logic circuitry;

if the divider value is an integer, then:

if the value contained in the clock divider counter is even, setting the reference value to 1; and

if the value contained in the clock divider counter is odd, setting the reference value to 1, except for every other assertion of the end count signal where the reference value is instead set to 0;

transitioning a toggle signal at a same edge of each pulse of the end count signal;

reloading the clock divider counter with most significant bits of the divider value as a function of the end count signal; and

generating a divided version of the clock signal as a function of the toggle signal.

2. The method of claim 1 , wherein the divider value is a mixed number having an integer part and a fractional part, with the fractional part being ½; and wherein the method also includes:

if the integer part of the divider value is even, setting the reference value to 1, except for every 4th assertion of the end count signal where the reference value is instead set to 0; and

if the integer part of the divider value is odd, setting the reference value to 1, except for:

every other assertion of the end count signal, where the reference value is instead set to 0; and

every 4th assertion of the end count signal, where the reference value is instead set to 0.

3. The method of claim 1 , wherein the divider value is a mixed number having an integer part and a fractional part, with the fractional part being ¼; and wherein the method also includes:

if the integer part of the divider value is even, setting the reference value to 1, except for:

every 4th assertion of the end count signal, where the reference value is instead set to 0; and

every 8th assertion of the end count signal, where the reference value is instead set to 0; and

if the integer part of the divider value is odd, setting the reference value to 1, except for:

every other assertion of the end count signal, where the reference value is instead set to 0;

every 4th assertion of the end count signal, where the reference value is instead set to 0; and

every 8th assertion of the end count signal, where the reference value is instead set to 0.

4. The method of claim 1 , wherein the divider value is a mixed number having an integer part and a fractional part, with the fractional part being ⅛; and wherein the method also includes:

if the integer part of the divider value is even, setting the reference value to 1, except for:

every 4th assertion of the end count signal, where the reference value is instead set to 0;

every 8th assertion of the end count signal, where the reference value is instead set to 0; and

every 16th assertion of the end count signal, where the reference value is instead set to 0; and

if the integer part of the divider value is odd, setting the reference value to 1, except for:

every other assertion of the end count signal, where the reference value is instead set to 0;

every 4th assertion of the end count signal, where the reference value is instead set to 0;

every 8th assertion of the end count signal, where the reference value is instead set to 0; and

every 16th assertion of the end count signal, where the reference value is instead set to 0.

5. The method of claim 1 , wherein the divider value is a mixed number having an integer part and a fractional part, with the fractional part being ½; and wherein if the integer part of the divider value is even, the method also includes setting the reference value to 1, except for every 4th assertion of the end count signal where the reference value is instead set to 0.

6. The method of claim 1 , wherein the divider value is a mixed number having an integer part and a fractional part, with the fractional part being ½; and wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1.

7. The method of claim 6 , wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1 except for every other assertion of the end count signal where the reference value is instead set to 0.

8. The method of claim 7 , wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1 except for every 4th assertion of the end count signal where the reference value is instead set to 0.

9. The method of claim 1 , wherein the divider value is a mixed number having an integer part and a fractional part, with the fractional part being ¼; and wherein if the integer part of the divider value is even, the method also includes setting the reference value to 1.

10. The method of claim 9 , wherein if the integer part of the divider value is even, the method also includes setting the reference value to 1, except for every 4th assertion of the end count signal, where the reference value is instead set to 0.

11. The method of claim 9 , wherein if the integer part of the divider value is even, the method also includes setting the reference value to 1, except for every 8th assertion of the end count signal, where the reference value is instead set to 0.

12. The method of claim 1 , wherein the divider value is a mixed number having an integer part and a fractional part, with the fractional part being ¼; and wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1.

13. The method of claim 12 , wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1, except for every other assertion of the end count signal, where the reference value is instead set to 0.

14. The method of claim 12 , wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1, except for every 4th assertion of the end count signal, where the reference value is instead set to 0.

15. The method of claim 12 , wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1, except for every 8th assertion of the end count signal, where the reference value is instead set to 0.

16. The method of claim 1 , wherein the divider value is a mixed number having an integer part and a fractional part, with the fractional part being ⅛; and wherein if the integer part of the divider value is even, the method also includes setting the reference value to 1.

17. The method of claim 16 , wherein if the integer part of the divider value is even, the method also includes setting the reference value to 1, except for every 4th assertion of the end count signal, where the reference value is instead set to 0.

18. The method of claim 16 , wherein if the integer part of the divider value is even, the method also includes setting the reference value to 1, except for every 8th assertion of the end count signal, where the reference value is instead set to 0.

19. The method of claim 16 , wherein if the integer part of the divider value is even, the method also includes setting the reference value to 1, except for every 16th assertion of the end count signal, where the reference value is instead set to 0.

20. The method of claim 1 , wherein the divider value is a mixed number having an integer part and a fractional part, with the fractional part being ⅛; and wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1.

21. The method of claim 20 , wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1 except for every other assertion of the end count signal, where the reference value is instead set to 0.

22. The method of claim 20 , wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1 except for every 4th assertion of the end count signal, where the reference value is instead set to 0.

23. The method of claim 20 , wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1 except for every 8th assertion of the end count signal, where the reference value is instead set to 0.

24. The method of claim 20 , wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1 except for every 16th assertion of the end count signal, where the reference value is instead set to 0.

25. A method, comprising:

loading a clock divider counter with most significant bits of a divider value;

decrementing the clock divider counter at a same edge of each pulse of a clock signal;

comparing a value contained in the clock divider counter to a reference value and generating an end count signal as a function of the value contained in the clock divider counter matching the reference value, using logic circuitry;

if the divider value is an integer, and if the value contained in the clock divider counter is even, setting the reference value to 1;

transitioning a toggle signal at a same edge of each pulse of the end count signal;

reloading the clock divider counter with most significant bits of the divider value as a function of the end count signal; and

generating a divided version of the clock signal as a function of the toggle signal.

26. The method of claim 25 , wherein the divider value is a mixed number having an integer part and a fractional part, with the fractional part being ½; and wherein if the integer part of the divider value is even, the method also includes setting the reference value to 1, except for every 4th assertion of the end count signal, where the reference value is instead set to 0.

27. The method of claim 25 , wherein the divider value is a mixed number having an integer part and a fractional part, with the fractional part being ¼; and wherein if the integer part of the divider value is even, the method also includes setting the reference value to 1.

28. The method of claim 27 , wherein if the integer part of the divider value is even, the method also includes setting the reference value to 1, except for every 4th assertion of the end count signal, where the reference value is instead set to 0.

29. The method of claim 27 , wherein if the integer part of the divider value is even, the method also includes setting the reference value to 1, except for every 8th assertion of the end count signal, where the reference value is instead set to 0.

30. The method of claim 25 , wherein the divider value is a mixed number having an integer part and a fractional part, with the fractional part being ⅛; and wherein if the integer part of the divider value is even, the method also includes setting the reference value to 1.

31. The method of claim 30 , wherein if the integer part of the divider value is even, the method also includes setting the reference value to 1, except for every 4th assertion of the end count signal, where the reference value is instead set to 0.

32. The method of claim 30 , wherein if the integer part of the divider value is even, the method also includes setting the reference value to 1, except for every 8th assertion of the end count signal, where the reference value is instead set to 0.

33. The method of claim 30 , wherein if the integer part of the divider value is even, the method also includes setting the reference value to 1, except for every 16th assertion of the end count signal, where the reference value is instead set to 0.

34. A method, comprising:

loading a clock divider counter with most significant bits of a divider value;

decrementing the clock divider counter at a same edge of each pulse of a clock signal;

comparing a value contained in the clock divider counter to a reference value and generating an end count signal as a function of the value contained in the clock divider counter matching the reference value, using logic circuitry;

if the divider value is an integer, and if the divider value is odd, setting the reference value to 1, except for every other assertion of the end count signal where the reference value is set to 0;

transitioning a toggle signal at a same edge of each pulse of the end count signal;

reloading the clock divider counter with most significant bits of the divider value as a function of the end count signal; and

generating a divided version of the clock signal as a function of the toggle signal.

35. The method of claim 34 , wherein the divider value is a mixed number having an integer part and a fractional part, with the fractional part being ½; and wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1.

36. The method of claim 35 , wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1 except for every other assertion of the end count signal, where the reference value is instead set to 0.

37. The method of claim 36 , wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1 except for every 4th assertion of the end count signal, where the reference value is instead set to 0.

38. The method of claim 34 , wherein the divider value is a mixed number having an integer part and a fractional part, with the fractional part being ¼; and wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1.

39. The method of claim 38 , wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1, except for every other assertion of the end count signal, where the reference value is instead set to 0.

40. The method of claim 38 , wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1, except for every 4th assertion of the end count signal, where the reference value is instead set to 0.

41. The method of claim 38 , wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1, except for every 8th assertion of the end count signal, where the reference value is instead set to 0.

42. The method of claim 34 , wherein the divider value is a mixed number having an integer part and a fractional part, with the fractional part being ⅛; and wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1.

43. The method of claim 42 , wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1 except for every other assertion of the end count signal, where the reference value is instead set to 0.

44. The method of claim 42 , wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1 except for every 4th assertion of the end count signal, where the reference value is instead set to 0.

45. The method of claim 42 , wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1 except for every 8th assertion of the end count signal, where the reference value is instead set to 0.

46. The method of claim 42 , wherein if the integer part of the divider value is odd, the method also includes setting the reference value to 1 except for every 16th assertion of the end count signal, where the reference value is instead set to 0.