Sensor integrated circuits and methods for safety critical applications
View Patent ↗A sensor integrated circuit can include sensors with differing levels of sensitivity, a first processing channel that responds to a first analog signal generated by a first sensor to generate a first processed signal, and a second processing channel that responds to a second analog signal generated by the second sensor to generate a second processed signal. Where the first sensor can include a pressure or optical sensing element, and the second sensor can include a pressure or optical sensing element. A checker circuit uses the processed signals to detect faults in the sensor integrated circuit.
1. A sensor integrated circuit comprising:
a substrate comprising a first cavity forming a first diaphragm that can be deformed by a pressure differential across the first diaphragm and a second cavity forming a second diaphragm that can be deformed by a pressure differential across the second diaphragm;
a first processing channel responsive to a first analog signal to generate a first processed signal, wherein the first analog signal is provided by a first sensing element positioned adjacent to the first diaphragm and configured to detect the pressure differential across the first diaphragm by detecting deformation of the first diaphragm;
a second processing channel responsive to a second analog signal to generate a second processed signal, wherein the second analog signal is provided by a second sensing element positioned adjacent to the second diaphragm and configured to detect the pressure differential across the second diaphragm by detecting deformation of the second diaphragm; and
a checker circuit responsive to the first processed signal and the second processed signal and configured to detect a fault in the sensor integrated circuit and generate a fault signal indicative of the fault when the first processed signal and the second processed signal differ from each other by more than a predetermined amount, wherein the checker circuit comprises a first sample circuit configured to sample the first processed signal and generate a first sampled signal, a second sample circuit configured to process the second processed signal and generate a second sampled signal, and a window comparator responsive to the first sampled signal and the second sampled signal and configured to generate the fault signal.
2. The sensor integrated circuit of claim 1 , where the substrate comprises a semiconductor wafer, a silicon-on-insulator (SOI) wafer, or a silicon wafer.
3. The sensor integrated circuit of claim 1 , where the substrate comprises a glass wafer.
4. The sensor integrated circuit of claim 1 , wherein a width of the first diaphragm is larger than a width of the second diaphragm.
5. The sensor integrated circuit of claim 1 , wherein a thickness of the first diaphragm is greater than a thickness of the second diaphragm.
6. The sensor integrated circuit of claim 1 , wherein the first diaphragm comprises a first material and the second diaphragm comprises a second material different from the first material.
7. The sensor integrated circuit of claim 6 , comprising a surface micromachined pressure sensor and a bulk micromachined pressure sensor.
8. The sensor integrated circuit of claim 1 , comprising multiple pressure sensing elements, wherein the first cavity comprises a first pressure sensing element, and the second cavity comprises a second pressure sensing element.
9. The sensor integrated circuit of claim 8 , wherein the first and second pressure sensing elements comprise magnetic field sensing elements and wherein a strength of a magnetic field detected by the first sensing element changes according to a deformation of the first diaphragm and a strength of a magnetic field detected by the second element changes according to a deformation of the second diaphragm.
10. The sensor integrated circuit of claim 9 , further comprising a ferromagnetic material adjacent to the first diaphragm and second diaphragm.
11. The sensor integrated circuit of claim 10 , further comprising one of a back-bias magnet, permanent magnet or coil adjacent to the magnetic field sensing elements.
12. The sensor integrated circuit of claim 8 , wherein the first and second pressure sensing elements comprise capacitive sensing elements and wherein an amount of capacitance detected by the first sensing element changes according to a deformation of the first diaphragm and an amount of capacitance detected by the second element changes according to a deformation of the second diaphragm.
13. The sensor integrated circuit of claim 1 , comprising multiple pressure sensing electrodes, wherein the first cavity comprises a first pair of pressure sensing electrodes, and the second cavity comprises a second pair of pressure sensing electrodes.
14. The sensor integrated circuit of claim 8 wherein the first and second pressure sensing elements comprise piezoelectric sensing elements and wherein an amount of voltage detected by the first sensing element changes according to a deformation of the first diaphragm and an amount of voltage detected by the second element changes according to a deformation of the second diaphragm.
15. The sensor integrated circuit of claim 14 , wherein the piezoelectric sensors comprise one of piezoresistors or piezotransistors.
16. The sensor integrated circuit of claim 1 , wherein a magnetic element is disposed in the first diaphragm and the second diaphragm.
17. The sensor integrated circuit of claim 16 , wherein the magnetic element that comprises one of a hard ferromagnetic material or a soft ferromagnetic material.
18. The sensor integrated circuit of claim 1 , wherein the first processing channel has a first accuracy and the second processing channel has a second accuracy different than the first accuracy.
19. The sensor integrated circuit of claim 1 , wherein the substrate is further configured to support the first sensing element and the second sensing element.
20. The sensor integrated circuit of claim 1 , wherein the substrate is further configured to support the first sensing element, and a second substrate separate from the substrate supporting the first sensing element, the second substrate configured to support the second sensing element.
21. The sensor integrated circuit of claim 20 , wherein the substrate is configured to support the first processing channel, the second processing channel and the checker circuit.
22. The sensor integrated circuit of claim 1 , wherein the substrate is formed either using at least one of a deep reactive ion etching process or an isotropic silicon wet etch process.
23. A sensor integrated circuit comprising:
a first processing channel responsive to a first analog signal to generate a first processed signal, wherein the first analog signal is provided by a first semiconductor structure configured to detect incident photons;
a second processing channel responsive to a second analog signal to generate a second processed signal, wherein the second analog signal is provided by a second semiconductor structure configured to detect incident photons; and
a checker circuit responsive to the first processed signal and the second processed signal and configured to detect a fault in the sensor integrated circuit and generate a fault signal indicative of the fault when the first processed signal and the second processed signal differ from each other by more than a predetermined amount, wherein the checker circuit comprises a first sample circuit configured to sample the first processed signal and generate a first sampled signal, a second sample circuit configured to process the second processed signal and generate a second sampled signal, and a window comparator responsive to the first sampled signal and the second sampled signal and configured to generate the fault signal.
24. The sensor integrated circuit of claim 23 , wherein the first semiconductor structure comprises a first material and the second semiconductor structure comprises a second material, wherein the first material is different from the second material.
25. The sensor integrated circuit of claim 23 , wherein the first semiconductor structure has a first surface area and the second semiconductor structure has a second surface area, wherein the first surface area is greater than the second surface area.
26. The sensor integrated circuit of claim 23 , comprising a substrate configured to support the first semiconductor structure and the second semiconductor structure.
27. The sensor integrated circuit of claim 23 , comprising a first substrate configured to support the first semiconductor structure, the first processing channel, the second processing channel and the checker circuit, and a second substrate configured to support the second semiconductor structure.