IP Library Granted Patent US 10,818,582
Granted Patent B2
US 10,818,582 · App. 16/680,649 · Granted Oct 27, 2020

Packaged semiconductor devices with laser grooved wettable flank and methods of manufacture

Inventors: Aira Lourdes Villamor (Lapu-Lapu, PH); Erwin Victor Cruz (Koronadal, PH); Geraldine Suico (Consolacion, PH); Silnore Sabando (Lapu-Lapu, PH)
Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
H01L23/49544H01L21/4821H01L21/4842H01L21/561H01L23/3157H01L23/492H01L23/4952H01L23/49548H01L23/49575H01L23/49582H01L23/3107
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Quick Facts
Patent No.
US 10,818,582
App. No.
16/680,649
Filed
Nov 12, 2019
Granted
Oct 27, 2020
Kind
B2
Art Unit
2896
USPC
257/666
Abstract

In a general aspect, a method for producing a packaged semiconductor device can include coupling a semiconductor device to a leadframe structure having a signal lead that is electrically coupled with the semiconductor device. The method can also include forming, with a laser, a groove in the signal lead, the groove having a first sidewall and a second sidewall, and applying solder plating to the signal lead, including the first sidewall and the second sidewall of the groove. The method can further include separating, at the groove, the signal lead into a first portion and a second portion, such that the second portion of the signal lead is separated from the metal leadframe structure.

Claims (51)

1. A method of producing a packaged semiconductor device, the method comprising:

coupling a semiconductor device to a metal leadframe structure, the metal leadframe structure having a signal lead that is electrically coupled with the semiconductor device;

forming, with a laser, a groove in the signal lead, the groove having a first sidewall and a second sidewall;

applying solder plating to the signal lead, including the first sidewall and the second sidewall of the groove; and

separating, at the groove, the signal lead into a first portion and a second portion, such that the second portion of the signal lead is separated from the metal leadframe structure,

the separating the signal lead defining a signal lead flank on an end of the first portion of the signal lead, the signal lead flank having a surface area, a first portion of the surface area of the signal lead flank being defined by the solder plating, and a second portion of the surface area of the flank of the signal lead being defined by exposed metal of the metal leadframe structure.

2. The method of claim 1 , wherein the groove is a V-shaped groove.

3. The method of claim 2 , wherein the separating the signal lead includes separating the signal lead at a bottom of the V-shaped groove.

4. The method of claim 1 , wherein the groove further includes a bottom surface disposed between the first sidewall and the second sidewall, the first sidewall having a first slope with respect to the bottom surface, and the second sidewall having a second slope with respect to the bottom surface, the second slope being different than the first slope.

5. The method of claim 1 , wherein the groove further includes a bottom surface disposed between the first sidewall and the second sidewall, the first sidewall and the second sidewall having a same slope with respect to the bottom surface.

6. The method of claim 1 , wherein:

the groove further includes a bottom surface disposed between the first sidewall and the second sidewall;

forming the groove includes forming a notch in the bottom surface, the notch being adjacent to the first sidewall; and

the separating the signal lead includes separating the signal lead at the notch.

7. The method of claim 1 , wherein:

the groove further includes a bottom surface disposed between the first sidewall and the second sidewall;

forming the groove includes:

forming a first notch in the bottom surface, the first notch being adjacent to the first sidewall; and

forming a second notch in the bottom surface, the second notch being adjacent to the second sidewall; and

the separating the signal lead includes separating the signal lead at the first notch and at the second notch.

8. The method of claim 1 , further comprising, prior to forming the groove in the signal lead, encapsulating at least a portion of the semiconductor device and at least a portion of the metal leadframe structure in a molding compound, such that a segment of the signal lead is exposed outside the molding compound, as surface of the molding compound defining a primary plane of the packaged semiconductor device.

9. The method of claim 8 , wherein a center portion of the surface of the exposed metal has a height along an axis that is approximately orthogonal with the primary plane of the packaged semiconductor device, the height of the center portion being greater than a height, along the axis that is approximately orthogonal with the primary plane of the packaged semiconductor device, of a portion of the surface of the exposed metal that is laterally disposed from the center portion of the surface of the exposed metal.

10. The method of claim 1 , wherein a perimeter of the exposed metal has at least one curved edge.

11. The method of claim 1 , wherein a perimeter of the exposed metal is semicircle shaped.

12. The method of claim 1 , wherein the exposed metal is surrounded by the solder plating.

13. A method of producing a packaged semiconductor device, the method comprising:

coupling a semiconductor device to a metal leadframe structure, the metal leadframe structure having a signal lead that is electrically coupled with the semiconductor device;

encapsulating at least a portion of the semiconductor device and at least a portion of the metal leadframe structure in a molding compound, a segment of the signal lead being exposed outside the molding compound;

forming, with a laser, a groove in the segment of the signal lead, the groove having a first sidewall, a second sidewall, and a bottom surface disposed between the first sidewall and the second sidewall;

applying solder plating to the segment of the signal lead, including the first sidewall, the second sidewall, and the bottom surface of the groove; and

separating, at the groove, the segment of the signal lead into a first portion and a second portion, such that the second portion of the segment of the signal lead is separated from the metal leadframe structure,

the separating the segment of the signal lead defines a signal lead flank on an end of the first portion of the segment of the signal lead, the signal lead flank having a surface area, a first portion of the surface area of the signal lead flank being defined by the solder plating, and a second portion of the surface area of the flank of the signal lead being defined by exposed metal of the metal leadframe structure.

14. The method of claim 13 , wherein the first sidewall has a first slope with respect to the bottom surface, and the second sidewall has a second slope with respect to the bottom surface, the second slope being different than the first slope.

15. The method of claim 13 , wherein the first sidewall and the second sidewall have a same slope with respect to the bottom surface.

16. The method of claim 13 , wherein:

forming the groove includes forming a notch in the bottom surface, the notch being adjacent to the first sidewall; and

the separating the signal lead includes separating the segment of the signal lead at the notch.

17. The method of claim 13 , wherein:

forming the groove includes:

forming a first notch in the bottom surface, the first notch being adjacent to the first sidewall; and

forming a second notch in the bottom surface, the second notch being adjacent to the second sidewall; and

the separating the signal lead includes separating the segment of the signal lead at the first notch and at the second notch.

18. A method of producing a packaged semiconductor device, the method comprising:

coupling a semiconductor device to a metal leadframe structure, the metal leadframe structure having a signal lead that is electrically coupled with the semiconductor device;

encapsulating at least a portion of the semiconductor device and at least a portion of the metal leadframe structure in a molding compound, a segment of the signal lead being exposed outside the molding compound;

forming, with a laser, a V-shaped groove in the segment of the signal lead;

applying solder plating to the segment of the signal lead, including the V-shaped groove; and

separating, at the V-shaped groove, the segment of the signal lead into a first portion and a second portion, such that the second portion of the segment of the signal lead is separated from the metal leadframe structure,

the separating the segment of the signal lead defines a signal lead flank on an end of the first portion of the segment of the signal lead, the signal lead flank having a surface area, a first portion of the surface area of the signal lead flank being defined by the solder plating, and a second portion of the surface area of the flank of the signal lead being defined by exposed metal of the metal leadframe structure.

19. The method of claim 18 , wherein the separating the segment of the signal lead includes separating the segment of the signal lead at a bottom of the V-shaped groove.

20. The method of claim 18 , wherein a perimeter of the surface of the exposed metal has at least one curved edge.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 054090, FRAME 0617 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064081/0167 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
SECURITY INTEREST Recorded Oct 16, 2020
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION; ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 054090/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 12, 2019
From: VILLAMOR, AIRA LOURDES; SUICO, GERALDINE; CRUZ, ERWIN VICTOR; SABANDO, SILNORE
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 050989/0282 →