Digital phase locked loop system

1. A system comprising:

a phase locked loop (PLL) circuit comprising:

a time-to-digital converter (TDC) configured to compare a reference clock signal to a feedback clock signal to generate an error signal;

a filter configured to generate a control signal based on the error signal;

a digitally controlled oscillator (DCO) configured to generate an output clock signal based on the control signal;

a multiplexer configured to provide the control signal or a preset value to the DCO based on a preset enable signal, wherein the preset value is determined based on a linearized two-point approximation of DCO characteristics between two frequency end-points of a frequency range that includes a desired output frequency of the output clock signal; and

a divider circuit configured to generate the feedback clock signal from the output clock signal based on ratio values; and

a control circuit coupled to the PLL circuit, the control circuit configured to:

receive data for the desired output frequency of the output clock signal;

determine first gain coefficients and second gain coefficients for the filter, the preset value for the DCO, and the ratio values for the divider circuit based on the data;

provide the preset enable signal to the multiplexer, the preset value to the DCO, the first gain coefficients to the filter, and the ratio values to the divider circuit while the PLL circuit operates in an open-loop configuration;

subsequently operate the PLL circuit in a closed-loop configuration by connecting the filter to the DCO to provide the control signal to the DCO; and

provide the second gain coefficients to the filter in response to detecting a phase lock of the PLL circuit operating in the closed-loop configuration.

2. The system of claim 1 , wherein each of the first gain coefficients is greater than a corresponding one of the second gain coefficients.

3. The system of claim 1 , wherein the control circuit is configured to:

determine the DCO characteristics; and

determine the first gain coefficients and the second gain coefficients based on the DCO characteristics.

4. The system of claim 1 , wherein the control circuit is configured to:

detect the phase lock of the PLL circuit based on the error signal; and

provide the first gain coefficients or the second gain coefficients to the filter based on the phase lock of the PLL circuit.

5. The system of claim 1 , wherein:

the first gain coefficients include a first proportional path gain coefficient and a first integral path gain coefficient;

the second gain coefficients include a second proportional path gain coefficient and a second integral path gain coefficient;

the first proportional path gain coefficient is greater than the second proportional path gain coefficient; and

the first integral path gain coefficient is greater than the second integral path gain coefficient.

6. A system comprising:

a control circuit coupled to a phase locked loop (PLL) circuit; and

a memory storing instructions that when executed by the control circuit cause the control circuit to:

receive data for a desired output frequency of an output clock of the PLL circuit;

determine a preset value for a digitally controlled oscillator (DCO) of the PLL circuit based on the data, wherein the preset value is determined based on a linearized two-point approximation of DCO characteristics between two frequency end-points of a frequency range that includes the desired output frequency of the output clock;

determine first gain coefficients and second gain coefficients for a filter of the PLL circuit based on the data;

determine ratio values for a divider circuit of the PLL circuit based on the data;

provide the preset value to the DCO, the first gain coefficients to the filter, and the ratio values to the divider circuit while the PLL circuit operates in an open-loop configuration;

subsequently operate the PLL circuit in a closed-loop configuration by connecting the filter to the DCO; and

provide the second gain coefficients to the filter in response to detecting a phase lock of the PLL circuit operating in the closed-loop configuration.

7. The system of claim 6 , wherein each of the first gain coefficients is greater than a corresponding one of the second gain coefficients.

8. The system of claim 6 , wherein the instructions cause the control circuit to:

determine the DCO characteristics; and

determine the first gain coefficients and the second gain coefficients based on the DCO characteristics.

9. The system of claim 6 , wherein the instructions cause the control circuit to:

receive an error signal from a time-to-digital converter (TDC) of the PLL circuit;

detect the phase lock of the PLL circuit based on the error signal; and

provide the first gain coefficients or the second gain coefficients to the filter based on the phase lock of the PLL circuit.

10. The system of claim 6 , wherein:

the first gain coefficients include a first proportional path gain coefficient and a first integral path gain coefficient;

the second gain coefficients include a second proportional path gain coefficient and a second integral path gain coefficient;

the first proportional path gain coefficient is greater than the second proportional path gain coefficient; and

the first integral path gain coefficient is greater than the second integral path gain coefficient.

11. A method comprising:

receiving data for a desired output frequency of an output clock of a phase locked loop (PLL) circuit;

determining a preset value for a digitally controlled oscillator (DCO) of the PLL circuit based on the data, wherein the preset value is determined based on a linearized two-point approximation of DCO characteristics between two frequency end-points of a frequency range that includes the desired output frequency of the output clock;

determining first gain coefficients and second gain coefficients for a filter of the PLL circuit based on the data;

determining ratio values for a divider circuit of the PLL circuit based on the data;

providing the preset value to the DCO, the first gain coefficients to the filter, and the ratio values to the divider circuit while the PLL circuit operates in an open-loop configuration;

subsequently operating the PLL circuit in a closed-loop configuration by connecting the filter to the DCO; and

providing the second gain coefficients to the filter in response to detecting a phase lock of the PLL circuit operating in the closed-loop configuration.

12. The method of claim 11 , wherein each of the first gain coefficients is greater than a corresponding one of the second gain coefficients.

13. The method of claim 11 , further comprising:

determining the DCO characteristics; and

determining the first gain coefficients and the second gain coefficients based on the DCO characteristics.

14. The method of claim 11 , further comprising:

receiving an error signal from a time-to-digital converter (TDC) of the PLL circuit;

detecting the phase lock of the PLL circuit based on the error signal; and

providing the first gain coefficients or the second gain coefficients to the filter based on the phase lock of the PLL circuit.

15. The method of claim 11 , wherein:

the first gain coefficients include a first proportional path gain coefficient and a first integral path gain coefficient;

the second gain coefficients include a second proportional path gain coefficient and a second integral path gain coefficient;

the first proportional path gain coefficient is greater than the second proportional path gain coefficient; and

the first integral path gain coefficient is greater than the second integral path gain coefficient.

16. The system of claim 1 further comprising a calibration module configured to:

calibrate the PLL circuit when power to the PLL circuit is turned on by allowing the PLL circuit lock at the two frequency end-points and storing a control word for each of the two frequency end-points; and

determining the linearized two-point approximation of DCO characteristics using the two frequency end-points and corresponding control words;

wherein the linearized two-point approximation of DCO characteristics is an inverse of a linearized DCO gain; and

wherein the linearized DCO gain is a ratio of a difference between the two control words to a difference between the two frequency end-points.

17. The system of claim 6 wherein the instructions cause the control circuit to:

calibrate the PLL circuit when power to the PLL circuit is turned on by allowing the PLL circuit to lock at the two frequency end-points and storing a control word for each of the two frequency end-points; and

determine the linearized two-point approximation of DCO characteristics using the two frequency end-points and corresponding control words;

wherein the linearized two-point approximation of DCO characteristics is an inverse of a linearized DCO gain; and

wherein the linearized DCO gain is a ratio of a difference between the two control words to a difference between the two frequency end-points.

18. The method of claim 11 further comprising:

calibrating the PLL circuit when power to the PLL circuit is turned on by allowing the PLL circuit to lock at the two frequency end-points and by storing a control word for each of the two frequency end-points; and

determining the linearized two-point approximation of DCO characteristics using the two frequency end-points and corresponding control words;

wherein the linearized two-point approximation of DCO characteristics is an inverse of a linearized DCO gain; and

wherein the linearized DCO gain is a ratio of a difference between the two control words to a difference between the two frequency end-points.