IP Library › Granted Patent US 11,016,145
Granted Patent B1
US 11,016,145 · App. 16/720,531 · Granted May 25, 2021

Fault test circuit using launch-off-shift scan

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Quick Facts
Patent No.
US 11,016,145
App. No.
16/720,531
Filed
Dec 19, 2019
Granted
May 25, 2021
Kind
B1
Art Unit
2112
USPC
714/727
Abstract

An integrated circuit sensor can have a test program generator that is configured to receive a portion of a scan vector, where the scan vector includes a test mode signal and a scan enable signal. The test program generator is configured to retrieve a launch-off-capture test sequence from the scan vector and use the launch-off-capture test sequence and the test mode signal to generate a launch-off-capture test signal. A test signal generator is configured to generate a launch-off-shift test signal using the launch-off-capture test signal and the scan enable signal. A built-in self-test circuit is configured to test the integrated circuit sensor using the launch-off-shift test signal.

Claims (45)

1. An integrated circuit sensor comprising:

a test program generator configured to receive a portion of a scan vector comprising a test mode signal and a scan enable signal, and the test program generator configured to retrieve a launch-off-capture test sequence from the scan vector and generate a launch-off-capture test signal using the launch-off-capture test sequence and the test mode signal;

a test clock signal generator configured to generate a launch-off-shift test signal using the launch-off-capture test signal and the scan enable signal;

a built-in self-test circuit configured to test the integrated circuit sensor using the launch-off-shift test signal; and

an oscillator configured to generate a master clock signal.

2. The integrated circuit sensor of claim 1 wherein the test program generator is configured to generate a launch-off-capture test signal using the launch-off-capture test sequence, the test mode signal and the master clock signal.

3. The integrated circuit sensor of claim 1 wherein the test program generator receives the scan vector from external test equipment.

4. The integrated circuit sensor of claim 3 wherein the scan vector comprises one or more test sequences and one or more expected test results.

5. The integrated circuit sensor of claim 1 wherein the test clock signal generator is configured to receive the scan vector.

6. The integrated circuit sensor of claim 1 wherein the test clock signal generator comprises a flip flop and an OR gate.

7. The integrated circuit sensor of claim 6 wherein the OR gate is configured to shift the launch-off-capture test signal to generate the launch-off-shift test signal.

8. A method for testing an integrated circuit sensor comprising:

receiving a scan vector comprising a test mode signal, a scan enable signal and a launch-off-capture test sequence;

generating a launch-off-capture test signal using the test mode signal, the launch-off-capture test sequence, and a master clock signal;

generating a launch-off-shift test signal using the launch-off-capture test signal and the scan enable signal; and

testing the integrated circuit sensor using the launch-off-shift test signal.

9. The method of claim 8 wherein receiving the scan vector comprises receiving the scan vector from external test equipment.

10. The method of claim 8 comprising:

receiving test results generated by a digital core of the integrated circuit sensor responsive to the launch-off-shift test signal, wherein the test results are associated with a launch-off-shift test mode.

11. An integrated circuit sensor comprising:

means for receiving a scan vector comprising a test mode signal, a scan enable signal and a launch-off-capture test sequence;

means for generating a launch-off-capture test signal using the test mode signal, the launch-off-capture test sequence, and a master clock signal;

means for generating a launch-off-shift test signal using the launch-off-capture test signal and the scan enable signal; and

means testing the integrated circuit sensor using the launch-off-shift test signal.

12. The integrated circuit of claim 11 wherein means for receiving the scan vector comprises means for receiving the scan vector from external test equipment.

13. The integrated circuit of claim 11 comprising:

means for receiving test results generated by a digital core of the integrated circuit sensor responsive to the launch-off-shift test signal, wherein the test results are associated with a launch-off-shift test mode.

14. An integrated circuit sensor comprising:

a test program generator configured to receive a portion of a scan vector comprising a test mode signal and a scan enable signal, and the test program generator configured to retrieve a launch-off-capture test sequence from the scan vector and generate a launch-off-capture test signal using the launch-off-capture test sequence and the test mode signal;

a test clock signal generator configured to generate a launch-off-shift test signal using the launch-off-capture test signal and the scan enable signal, wherein the test clock signal generator comprises a flip flop and an OR gate; and

a built-in self-test circuit configured to test the integrated circuit sensor using the launch-off-shift test signal.

15. The integrated circuit sensor of claim 14 comprising an oscillator configured to generate a master clock signal.

16. The integrated circuit sensor of claim 15 wherein the test program generator is configured to generate a launch-off-capture test signal using the launch-off-capture test sequence, the test mode signal and the master clock signal.

17. The integrated circuit sensor of claim 14 wherein the test program generator receives the scan vector from external test equipment.

18. The integrated circuit sensor of claim 17 wherein the scan vector comprises one or more test sequences and one or more expected test results.

19. The integrated circuit sensor of claim 14 wherein the test clock signal generator is configured to receive the scan vector.

20. The integrated circuit sensor of claim 14 wherein the OR gate is configured to shift the launch-off-capture test signal to generate the launch-off-shift test signal.

21. A method for testing an integrated circuit sensor comprising:

receiving a scan vector comprising a test mode signal, a scan enable signal and a launch-off-capture test sequence;

generating a launch-off-capture test signal using the test mode signal and the launch-off-capture test sequence;

generating a launch-off-shift test signal using the launch-off-capture test signal and the scan enable signal;

testing the integrated circuit sensor using the launch-off-shift test signal; and

receiving test results generated by a digital core of the integrated circuit sensor responsive to the launch-off-shift test signal, wherein the test results are associated with a launch-off-shift test mode.

22. The method of claim 21 wherein generating the launch-off-capture test signal further comprises generating the launch-off-capture test signal using the test mode signal, the launch-off-capture test sequence and a master clock signal.

23. The method of claim 21 wherein receiving the scan vector comprises receiving the scan vector from external test equipment.