Safety mechanism for digital reset state
A system is provided, comprising: a plurality of flip-flops that are configured to receive a reset signal, each of the plurality of flip-flops having a respective output port, and each of the plurality of flip-flops being configured to assume a respective default state when the reset signal is set to a predetermined value; and a reset monitor circuit that is coupled to the respective output port of each of the plurality of flip-flops, the reset monitor circuit being configured to generate a status signal indicating whether each of the flip-flops has assumed the flip-flop's respective default state after the reset signal is set to the predetermined value, wherein assuming a respective default state by each of the plurality of flip-flops results in a predetermined bit string being stored in the plurality of flip-flops.
1. A system, comprising:
a plurality of flip-flops that are configured to receive a reset signal, each of the plurality of flip-flops having a respective output port, and each of the plurality of flip-flops being configured to assume a respective default state when the reset signal is set to a predetermined value; and
a reset monitor circuit that is coupled to the respective output port of each of the plurality of flip-flops, the reset monitor circuit being configured to generate a status signal indicating whether each of the flip-flops has assumed the flip-flop's respective default state after the reset signal is set to the predetermined value,
wherein assuming a respective default state by each of the plurality of flip-flops results in a predetermined bit string being stored in the plurality of flip-flops.
2. The system of claim 1 , wherein the respective default state of at least one of the plurality of flip-flops includes a first state and the respective default state of at least another one of the plurality of flip-flops includes a second state that is different from the first state.
3. The system of claim 1 , wherein the predetermined bit string includes one or more 1s and one or more 0s.
4. The system of claim 1 , wherein the plurality of flip-flops and the reset monitor circuit are part of a scan chain for testing the system.
5. The system of claim 1 , wherein:
each of the plurality of flip-flops is configured to output a respective output signal via the flip-flop's respective output port;
the respective output signal of at least one of the plurality of flip-flops is inverted prior to being processed by the reset monitor circuit, and the respective output signal of at least another one of the plurality of flip-flops is not inverted prior to being processed by the reset monitor circuit.
6. The system of claim 1 , wherein the plurality of flip-flops includes one or more type-1 flip-flops and one or more type-2 flip-flops, such that:
(i) each of the type-1 flip-flops includes a reset port that is arranged to receive the reset signal, and the default state of each of the plurality of type-1 flip-flops includes a state in which the type-1 flip-flop outputs an output signal having a logic-low value;
(ii) each of the type-2 flip-flops includes a set port that is arranged to receive the reset signal, and the default state of each of the plurality of type-2 flip-flops includes a state in which the type-2 flip-flop outputs an output signal having a logic-high value.
7. The system of claim 1 , further comprising a transducer that is operatively coupled to a signal processing circuitry, wherein the plurality of flip-flops and the reset monitor circuit are part of a scan chain for testing the signal processing circuitry.
8. The system of claim 1 , wherein each of the plurality of flip-flops includes a D-type flip-flop.
9. The system of claim 1 , further comprising a testing circuitry configured to:
detect whether the reset signal is set to the predetermined value; and
transition the system into a predetermined state when the status signal generated by the reset monitor circuit indicates that at least one of the plurality of flip-flops has failed to assume the flip-flop's respective default state in response to the reset signal being set to the predetermined value.
10. The system of claim 9 , wherein transitioning the system into the predetermined state includes outputting a signal indicating that one or more of the plurality of flip-flops have failed.
11. A system, comprising:
a plurality of flip-flops that are configured to receive a reset signal, each of the plurality of flip-flops having a respective output port, and each of the plurality of flip-flops being configured to assume a respective default state when the reset signal is set to a predetermined value;
a reset monitor circuit that is coupled to the respective output port of each of the plurality of flip-flops, the reset monitor circuit being configured to generate a status signal indicating whether each of the flip-flops has assumed the flip-flop's respective default state after the reset signal is set to the predetermined value; and
a testing circuitry configured to detect whether the reset signal is set to the predetermined value, and transition the system into a predetermined state when the status signal generated by the reset monitor circuit indicates that at least one of the plurality of flip-flops has failed to assume the flip-flop's respective default state in response to the reset signal being set to the predetermined value.
12. The system of claim 11 , wherein transitioning the system into the predetermined state includes outputting a signal indicating that one or more of the plurality of flip-flops have failed.
13. The system of claim 11 , wherein assuming a respective default state by each of the plurality of flip-flops results in a predetermined bit string being stored in the plurality of flip-flops.
14. The system of claim 11 , wherein the plurality of flip-flops includes one or more type-1 flip-flops and one or more type-2 flip-flops, such that:
(i) each of the type-1 flip-flops includes a reset port that is arranged to receive the reset signal, and the default state of each of the plurality of type-1 flip-flops includes a state in which the type-1 flip-flop outputs an output signal having a logic-low value;
(ii) each of the type-2 flip-flops includes a set port that is arranged to receive the reset signal, and the default state of each of the plurality of type-2 flip-flops includes a state in which the type-2 flip-flop outputs an output signal having a logic-high value.
15. The system of claim 11 , wherein the plurality of flip-flops and the reset monitor circuit are part of a scan chain for testing the system.
16. A sensor comprising:
a transducer;
a processing circuitry coupled to the transducer, the processing circuitry being configured to digitally process a signal that is generated using the transducer;
a plurality of flip-flops that are configured to receive a reset signal, each of the plurality of flip-flops having a respective output port, and each of the plurality of flip-flops being configured to assume a respective default state when the reset signal is set to a predetermined value; and
a reset monitor circuit that is coupled to the respective output port of each of the plurality of flip-flops, the reset monitor circuit being configured to generate a status signal indicating whether each of the flip-flops has assumed the flip-flop's respective default state after the reset signal is set to the predetermined value;
a testing circuitry configured to detect whether the reset signal is set to the predetermined value, and transition the sensor into a predetermined state when the status signal indicates that at least one of the plurality of flip-flops has failed to assume the flip-flop's respective default state in response to the reset signal being set to the predetermined value,
wherein assuming a respective default state by each of the plurality of flip-flops results in the plurality of flip-flops being transitioned into a state in which a predetermined bit string is stored in the plurality of flip-flops.
17. The sensor of claim 16 , wherein transitioning the sensor into the predetermined state includes outputting a signal indicating that one or more of the plurality of flip-flops have failed.
18. The sensor of claim 16 , wherein the respective default state of at least one of the plurality of flip-flops includes a first state and the respective default state of at least another one of the plurality of flip-flops includes a second state that is different from the first state.
19. The sensor of claim 16 , wherein:
each of the plurality of flip-flops is configured to output a respective output signal via the flip-flop's respective output port;
the respective output signal of at least one of the plurality of flip-flops is inverted prior to being processed by the reset monitor circuit, and the respective output signal of at least another one of the plurality of flip-flops is not inverted prior to being processed by the reset monitor circuit.
20. The sensor of claim 16 , wherein the plurality of flip-flops includes one or more type-1 flip-flops and one or more type-2 flip-flops, such that:
(i) each of the type-1 flip-flops includes a reset port that is arranged to receive the reset signal, and the default state of each of the plurality of type-1 flip-flops includes a state in which the type-1 flip-flop outputs an output signal having a logic-low value;
(ii) each of the type-2 flip-flops includes a set port that is arranged to receive the reset signal, and the default state of each of the plurality of type-2 flip-flops includes a state in which the type-2 flip-flop outputs an output signal having a logic-high value.