IP Library › Granted Patent US 11,231,997
Granted Patent B2
US 11,231,997 · App. 16/914,764 · Granted Jan 25, 2022

Storage system and method for balanced quad-level cell (QLC) coding with margin for an internal data load (IDL) read

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Quick Facts
Patent No.
US 11,231,997
App. No.
16/914,764
Filed
Jun 29, 2020
Granted
Jan 25, 2022
Kind
B2
Art Unit
2112
USPC
714/764
Abstract

A storage system and method for balanced quad-level cell (QLC) coding with margin for an internal data load (IDL) read are provided. In one example, an MLC-Fine programming approach uses a balanced 3-4-4-4 coding, where the data is encoded by assigning a unique binary sequence per state. The IDL read is supported by using a unique 3-4-4-4 coding that provides at least a three-state gap between the MLC states, while using the same ECC redundancy per page. This allows for a reduced write buffer by supporting the IDL read and provides a balanced bit error rate (BER) due to the balanced mapping.

Claims (36)

1. A storage system comprising:

a memory; and

a controller configured to:

apply a quad-level cell (QLC) 3-4-4-4 grey code to lower and middle pages of data, which induce a multi-level cell grey coding with a margin of at least a two state difference;

program the lower and middle pages of data in the memory using a multi-level cell programming operation;

read the programming of the lower and middle pages of data in the memory; and

program upper and top pages of data in the memory to induce a quad-level cell (QLC) distribution using the read lower and middle pages.

2. The storage system of claim 1 , wherein the read data is retrieved without using error correction.

3. The storage system of claim 1 , wherein the lower, middle pages are read from the memory array without retrieving them from a write buffer in the controller.

4. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.

5. The storage system of claim 1 , wherein the storage system is configured to be embedded in a host.

6. The storage system of claim 1 , wherein the storage system is configured to be removably connected to a host.

7. In a storage system comprising a memory and a controller, a method comprising:

programming lower and middle pages of data in the memory using a multi-level cell programming operation;

generating an exclusive-or of the lower and middle pages of data in the memory;

storing the exclusive-or of the lower and middle pages of data in the storage system;

reading the programming of the lower and middle pages of data in the memory;

decoding the lower and middle pages of data using the exclusive-or of the lower and middle pages of data; and

programming upper and top pages of data in the memory.

8. The method of claim 7 , wherein the exclusive-or of the lower and middle pages of data is stored in a temporary location in the storage system.

9. The method of claim 7 , wherein the read data is retrieved without using error correction.

10. The method of claim 7 , wherein the lower, middle pages are read from the memory array without retrieving them from a write buffer in the controller.

11. The method of claim 7 , wherein the memory comprises a three-dimensional memory.

12. The method of claim 7 , wherein the storage system is configured to be embedded in a host.

13. The method of claim 7 , wherein the storage system is configured to be removably connected to a host.

14. A storage system comprising:

a memory;

means for applying a quad-level cell (QLC) 3-4-4-4 grey code to lower and middle pages of data, which induce a multi-level cell grey coding with a margin of at least a two state difference;

means for programming the lower and middle pages of data in the memory using a multi-level cell programming operation;

means for reading the programming of the lower and middle pages of data in the memory; and

means for programming upper and top pages of data in the memory to induce a quad-level cell (QLC) distribution.

15. The storage system of claim 14 , wherein the read data is retrieved without using error correction.

16. The storage system of claim 14 , wherein the lower, middle pages are read from the memory array without retrieving them from a write buffer in the controller.

17. The storage system of claim 14 , wherein the memory comprises a three-dimensional memory.

18. The storage system of claim 14 , wherein the storage system is configured to be embedded in a host.

19. The storage system of claim 14 , wherein the storage system is configured to be removably connected to a host.