IP Library Granted Patent US 11,342,189
Granted Patent B2
US 11,342,189 · App. 16/985,995 · Granted May 24, 2022

Semiconductor packages with die including cavities and related methods

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,342,189
App. No.
16/985,995
Filed
Aug 5, 2020
Granted
May 24, 2022
Kind
B2
Examiner
ARORA, AJAY
Art Unit
2892
USPC
438/106
Abstract

Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.

Claims (36)

1. A method of forming a semiconductor package, the method comprising:

forming a plurality of notches into the first side of a semiconductor substrate;

forming an organic material over the first side of the semiconductor substrate and into the plurality of notches;

forming a cavity into each of a plurality of semiconductor die comprised in the semiconductor substrate;

applying a backmetal into the cavity in each of the plurality of semiconductor die comprised in the semiconductor substrate; and

singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.

2. The method of claim 1 , further comprising stress relief etching the second side of the semiconductor substrate.

3. The method of claim 1 , further comprising thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches prior to forming the cavity into each of the plurality of semiconductor die.

4. The method of claim 3 , wherein forming the organic material over the first side of the semiconductor substrate further comprises forming a permanent die support structure, a temporary die support structure, or any combination thereof.

5. The method of claim 1 , further comprising filling the cavity of each semiconductor die with a conductive metal.

6. The method of claim 1 , further comprising filling the cavity of each semiconductor die with a conductive metal that contacts only a largest planar surface of the cavity.

7. A method of forming a semiconductor package, the method comprising:

forming a plurality of notches into the first side of a semiconductor substrate;

forming an organic material over the first side of the semiconductor substrate and the plurality of notches;

thinning a second side of the semiconductor substrate opposite the first side toward the plurality of notches to expose the organic material in the plurality of notches;

forming a cavity into each of a plurality of semiconductor die comprised in the semiconductor substrate;

applying a backmetal over the second side of the semiconductor substrate; and

singulating the semiconductor substrate into a plurality of semiconductor packages.

8. The method of claim 7 , further comprising stress relief etching the second side of the semiconductor substrate.

9. The method of claim 7 , wherein forming the cavity into each of the plurality of semiconductor die further comprises forming using etching.

10. The method of claim 7 , wherein forming the organic material over the first side of the semiconductor substrate further comprises forming a permanent die support structure, a temporary die support structure, or any combination thereof.

11. The method of claim 7 , further comprising further comprising filling the cavity of each semiconductor die with a conductive metal.

12. The method of claim 7 , further comprising filling the cavity of each semiconductor die with a conductive metal that contacts only a largest planar surface of the cavity.

13. The method of claim 7 , further comprising forming a plurality of electrical connectors on the first side of the semiconductor substrate.

14. A method of forming a semiconductor package, the method comprising:

forming an organic material over the first side of a semiconductor substrate and a plurality of notches in the semiconductor substrate;

forming a cavity into each of a plurality of semiconductor die comprised in the semiconductor substrate;

applying a backmetal into the cavity in each of the plurality of semiconductor die comprised in the semiconductor substrate; and

singulating the semiconductor substrate into a plurality of semiconductor packages;

wherein the organic material extends one of partially across a thickness of each of the plurality of semiconductor die or fully across the thickness of each of the plurality of semiconductor die.

15. The method of claim 14 , wherein the plurality of notches are die streets between a plurality of die comprised on the semiconductor die.

16. The method of claim 14 , further comprising thinning a second side of the semiconductor substrate opposite the first side toward the plurality of notches prior to forming the cavity into each of the plurality of semiconductor die.

17. The method of claim 16 , wherein forming the organic material over the first side of the semiconductor substrate further comprises forming a permanent die support structure, a temporary die support structure, or any combination thereof.

18. The method of claim 14 , further comprising filling the cavity of each semiconductor die with a conductive metal.

19. The method of claim 14 , further comprising filling the cavity of each semiconductor die with a conductive metal that contacts only a largest planar surface of the cavity.

20. The method of claim 14 , further comprising forming a plurality of electrical connectors on the first side of the semiconductor substrate.