Silicon on insulator device with partially recessed gate
View Patent ↗Transistors having partially recessed gates are constructed on silicon-on-insulator (SOI) semiconductor wafers provided with a buried oxide layer (BOX), for example, FD-SOI and UTBB devices. An epitaxially grown channel region relaxes constraints on the design of doped source and drain profiles. Formation of a partially recessed gate and raised epitaxial source and drain regions allow further improvements in transistor performance and reduction of short channel effects such as drain induced barrier lowering (DIBL) and control of a characteristic subthreshold slope. Gate recess can be varied to place the channel at different depths relative to the dopant profile, assisted by advanced process control. The partially recessed gate has an associated high-k gate dielectric that is initially formed in contact with three sides of the gate. Subsequent removal of the high-k sidewalls and substitution of a lower-k silicon nitride encapsulant lowers capacitance between the gate and the source and drain regions.
1. A transistor, comprising:
a substrate;
a semiconductor body over the substrate;
a doped drain region positioned in the semiconductor body;
a doped source region positioned in the semiconductor body and separated from the doped drain region;
a channel region extending between the source and drain regions, the channel region having a different doping property from those of the doped drain region and the doped source region and at least partially over the doped drain region and the doped source region respectively, with respect to the substrate;
a gate stack partially recessed in the semiconductor body to a recess depth below a top surface of the semiconductor body, the gate stack including:
a gate dielectric in contact with the channel region, the gate dielectric having a dielectric length in a first direction; and
a conductive gate having a gate length in the first direction that exceeds the dielectric length by a distance that defines an undercut region, the conductive gate having a top surface, sidewalls, and an underside; and
a single, continuous encapsulant in contact with the top surface, sidewalls, and underside of the conductive gate, the single, continuous encapsulant including an extension portion positioned below the top surface of the semiconductor body, extending in the undercut region, and in contact with the underside of the conductive gate and an edge surface of the gate dielectric and in contact with both the channel region and the doped source region from a vertical direction with respect to the substrate.
2. The transistor of claim 1 , further comprising:
raised source and drain region positioned above the top surface of the semiconductor body and contacting the doped source and drain regions, respectively; and
first and second metal contacts connected to the raised source and drain regions, respectively.
3. The transistor of claim 2 , wherein the raised doped source and drain regions are made of epitaxial SiC.
4. The transistor of claim 2 , wherein the first metal contact contacts a first lateral side and a top side of the encapsulant and the second metal contact contacts a second lateral side and the top side of the encapsulant.
5. The transistor of claim 1 , wherein the channel region is an epitaxial channel made of silicon germanium.
6. The transistor of claim 1 , wherein the semiconductor body includes:
a semiconductor substrate;
a semiconductor layer; and
a buried insulating layer positioned between the semiconductor layer and the semiconductor substrate, wherein the doped source and drain regions are positioned in the semiconductor layer and extend to the buried insulating layer.
7. The method of claim 1 , wherein the gate dielectric is made of a material having a dielectric constant greater than about 4.0.
8. The transistor of claim 1 , wherein the conductive gate includes a metal barrier layer made of a metal silicide that includes one or more of titanium, titanium nitride, titanium carbide, titanium tungsten, tantalum, or tantalum nitride.
9. The transistor of claim 1 , wherein the conductive gate includes one or more of aluminum, tungsten, silver, platinum, gold, or copper.
10. A transistor, comprising:
a substrate that includes a buried insulating layer and a semiconductor layer on the buried insulating layer;
a drain region that extends downward to the buried insulating layer;
a source region that extends downward to the buried insulating layer and separated from the drain region;
a channel extending between the source and drain regions, the channel region having a different doping property from those of the doped drain region and the doped source region and at least partially over the doped drain region and the doped source region respectively, with respect to the substrate;
a gate stack partially recessed to a recess depth below the top surface of the substrate, the gate stack including:
a gate dielectric in contact with the channel, the gate dielectric having a dielectric length in a first direction; and
a conductive gate having a gate length in the first direction that exceeds the dielectric length by a distance that defines an undercut region, the conductive gate having a top surface, sidewalls, and an underside; and
a single, continuous encapsulant in contact with the top surface, sidewalls, and underside of the conductive gate, the single, continuous encapsulant including an extension portion positioned below the top surface of the semiconductor body, extending in the undercut region, and in contact with the underside of the conductive gate and an edge surface of the gate dielectric and in contact with both the channel region and the doped source region from a vertical direction with respect to the substrate.
11. The transistor of claim 10 , wherein the source region and drain region extend above a top surface of the substrate.
12. The transistor of claim 10 , further comprising first and second metal contacts connected to the doped source and drain regions, respectively, wherein the first metal contact contacts a first lateral side and a top side of the encapsulant and the second metal contact contacts a second lateral side and the top side of the encapsulant.
13. The transistor of claim 10 , wherein the channel is an epitaxial channel made of silicon germanium.
14. The transistor of claim 10 , wherein the gate dielectric is made of a material having a dielectric constant greater than about 4.0.
15. A transistor, comprising:
a substrate that includes a buried insulating layer and a silicon layer on the buried insulating layer;
a drain region that extends downward to the buried insulating layer;
a source region that extends downward to the buried insulating layer, and separated from the drain region;
an epitaxial channel extending between the source and drain regions, the epitaxial channel being made of silicon germanium, the channel region having a different doping property from those of the doped drain region and the doped source region and at least partially over the doped drain region and the doped source region, respectively, with respect to the substrate;
a gate stack including:
a gate dielectric in contact with the epitaxial channel, the gate dielectric having a dielectric length in a first direction; and
a conductive gate having a gate length in the first direction that exceeds the dielectric length by a distance that defines an undercut region, the conductive gate having a top surface, sidewalls, and an underside; and
a single, continuous encapsulant in contact with the top surface, sidewalls, and underside of the conductive gate, the encapsulant including an extension portion positioned below the top surface of the semiconductor body, extending in the undercut region, and in contact with the underside of the conductive gate and an edge surface of the gate dielectric and in contact with both the channel region and the doped source region from a vertical direction with respect to the substrate.
16. The transistor of claim 15 , further comprising:
raised source and drain regions positioned above the top surface of the semiconductor body and contacting the doped source and drain regions, respectively.
17. The transistor of claim 16 , further comprising:
first and second metal contacts connected to the raised source and drain regions, respectively.
18. The transistor of claim 17 , wherein the first metal contact contacts a first lateral side and a top side of the encapsulant and the second metal contact contacts a second lateral side and the top side of the encapsulant.
19. The transistor of claim 16 , wherein the raised doped source and drain regions are made of epitaxial SiC.
20. The transistor of claim 15 , wherein the gate stack is partially recessed in the semiconductor body to a recess depth below a top surface of the semiconductor body.