IP Library Granted Patent US 11,437,426
Granted Patent B2
US 11,437,426 · App. 16/672,639 · Granted Sep 6, 2022

Image sensor chip scale packages and related methods

Inventor: Swarnal Borthakur (Boise, ID)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L27/14685H01L22/32H01L23/3171H01L24/04H01L27/14634H01L27/14689
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Quick Facts
Patent No.
US 11,437,426
App. No.
16/672,639
Filed
Nov 4, 2019
Granted
Sep 6, 2022
Kind
B2
Examiner
LEE, CHEUNG
Art Unit
2826
USPC
438/65
Abstract

Methods of forming an image sensor chip scale package. Implementations may include providing a semiconductor wafer having a pixel array, forming a first cavity through the wafer and/or one or more layers coupled over the wafer, filling the first cavity with a fill material, planarizing the fill material and/or the one or more layers to form a first surface of the fill material coplanar with a first surface of the one or more layers, and bonding a transparent cover over the fill material and the one or more layers. The bond may be a fusion bond between the transparent cover and a passivation oxide; a fusion bond between the transparent cover and an anti-reflective coating; a bond between the transparent cover and an organic adhesive coupled over the fill material, and/or; a bond between a first metallized surface of the transparent cover and a metallized layer coupled over the wafer.

Claims (29)

1. An image sensor chip scale package (CSP) comprising:

a die comprising one or more layers thereon, an array of pixels, and an array of microlenses;

a cavity through one of the die or the one or more layers, the cavity comprising a fill material; and

an optically transmissive cover bonded over the fill material and over the one or more layers using one of a fusion bond between the optically transmissive cover and a passivation oxide or a fusion bond between the optically transmissive cover and anti-reflective coating;

wherein the cavity is configured to comprise an entire width of a conductive pad.

2. The image sensor CSP of claim 1 , wherein the fill material comprises an oxide.

3. The image sensor CSP of claim 1 , wherein the optically transmissive cover comprises one of a second cavity or a lens.

4. The image sensor CSP of claim 1 , further comprising a plurality of stacked die.

5. The image sensor CSP of claim 1 , further comprising a second cavity comprised through one of the die or the one or more layers and the second cavity is filled with one of the fill material or a second fill material.

6. The image sensor CSP of claim 1 , wherein a first surface of the fill material is coplanar with a plane that intersects a color filter array (CFA) of the image sensor CSP.

7. An image sensor chip scale package (CSP) comprising:

a die comprising an array of pixels and an array of microlenses coupled thereto;

a first cavity through one of the die and one or more layers coupled over the die; the first cavity comprising a fill material;

an optically transmissive cover bonded over the fill material and over the one or more layers; and

one or more openings comprised in a layer defining the first cavity to test one or more electrical functions of the image sensor CSP.

8. The image sensor CSP of claim 7 , further comprising a second cavity comprised through one of the die or the one or more layers, the second cavity filled with one of the fill material or a second fill material.

9. The image sensor CSP of claim 7 , wherein the optically transmissive cover comprises one of a second cavity or a lens.

10. A method of forming an image sensor chip scale package (CSP) comprising:

forming a cavity through one of a wafer or one or more layers comprised in the wafer;

forming a conductive pad in the cavity, wherein an entire width of the conductive pad is formed within the cavity;

applying a fill material over the conductive pad and in the cavity;

bonding an optically transmissive cover over the fill material, over the one or more layers, and over an array of microlenses coupled to the one or more layers; and

singulating the wafer into a plurality of image sensor chip scale packages;

wherein the cavity comprises at least a portion of a testing contact, the testing contact configured to test one or more electrical functions of the image sensor CSP.

11. The method of claim 10 , further comprising planarizing the fill material to form a surface coplanar with a first surface of the one or more layers.

12. The method of claim 10 , further comprising forming a second cavity through one of the wafer and the one or more layers, the second cavity filled with one of the fill material or a second fill material.

13. The method of claim 12 , further comprising planarizing one of the fill material or the second fill material to form a second surface coplanar with a first surface of the fill material.

14. The method of claim 10 , wherein the cavity is a first cavity and the optically transmissive cover is bonded over a full diameter of the first cavity and over at least a portion of a diameter of a second cavity.

15. The method of claim 10 , wherein the optically transmissive cover comprises one of a cavity or a global lens.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 054090, FRAME 0617 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064081/0167 →
SECURITY INTEREST Recorded Oct 16, 2020
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION; ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 054090/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 4, 2019
From: BORTHAKUR, SWARNAL
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 050901/0502 →