IP Library Granted Patent US 11,482,629
Granted Patent B2
US 11,482,629 · App. 16/456,621 · Granted Oct 25, 2022

Solar cell

Inventors: Jaewon Chang (Seoul, KR); Kyungjin Shim (Seoul, KR); Hyunjung Park (Seoul, KR); Junghoon Choi (Seoul, KR)
Assignee: LG ELECTRONICS INC.
H01L31/02167H01L31/0747H01L31/186H01L31/1864H01L31/1868C23C16/24H01L21/4867Y02E10/50
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Quick Facts
Patent No.
US 11,482,629
App. No.
16/456,621
Filed
Jun 28, 2019
Granted
Oct 25, 2022
Kind
B2
Art Unit
1726
USPC
438/98
Abstract

A method for manufacturing a solar cell, includes providing a silicon substrate, forming an oxide layer on a first surface of the silicon substrate, forming a doped polycrystalline silicon layer on the oxide layer, forming a passivation layer on the doped polycrystalline silicon layer, printing a metal paste on the passivation layer, and forming a metal contact connected to the doped polycrystalline silicon layer by firing the metal paste to penetrate the passivation layer.

Claims (43)

1. A method for manufacturing a solar cell, the method comprising:

providing a silicon substrate;

forming an oxide layer on a first surface of the silicon substrate;

forming a doped polycrystalline silicon layer on the oxide layer;

forming a passivation layer on the doped polycrystalline silicon layer;

printing a metal paste on the passivation layer;

forming a metal contact connected to the doped polycrystalline silicon layer by firing the metal paste to penetrate the passivation layer; and

forming an additional doped region at a portion of the silicon substrate facing the oxide layer by diffusing a dopant of the doped polycrystalline silicon layer into the silicon substrate through a thermal treatment of the doped polycrystalline silicon layer,

wherein the oxide layer has a thickness of 0.5 nm to 5 nm, and the doped polycrystalline silicon layer has a thickness of 50 nm to 500 nm, and

wherein the metal contact physically contacts the doped polycrystalline silicon layer and does not directly physically contact the additional doped region.

2. The method according to claim 1 , wherein the firing of the metal paste is performed by a fire through.

3. The method according to claim 1 , wherein the firing of the metal paste is performed by a laser firing contact.

4. The method according to claim 1 , wherein an opening through the passivation layer is formed during the firing of the metal paste.

5. The method according to claim 1 , further comprising:

forming an additional layer on the passivation layer.

6. The method according to claim 5 , wherein an opening through the passivation layer and the additional layer is formed during the firing of the metal paste.

7. The method according to claim 1 , wherein the doped polycrystalline silicon layer is formed by using a deposition method.

8. The method according to claim 1 , wherein the doped polycrystalline silicon layer is formed by using a plasma-enhanced chemical vapor deposition chemical (PECVD).

9. The method according to claim 1 , wherein, in the forming of the doped polycrystalline silicon layer, the dopant is doped when a polycrystalline silicon layer is formed.

10. The method according to claim 1 , wherein the doped polycrystalline silicon layer is formed by forming a polycrystalline silicon layer and then doping the polycrystalline silicon layer with the dopant.

11. The method according to claim 1 , further comprising:

forming a doped region at a second surface of the silicon substrate.

12. The method according to claim 11 , wherein the doped region has a conductive type opposite to a conductive type of the doped polycrystalline silicon layer.

13. The method according to claim 11 , wherein the doped region is formed by diffusing a dopant into the silicon substrate.

14. The method according to claim 11 , further comprising:

forming a second oxide layer before the forming of the doped region,

wherein the doped region is formed on the second oxide layer and formed of another doped polycrystalline layer.

15. The method according to claim 11 , wherein the first surface is a back surface of the silicon substrate.

16. The method according to claim 15 , further comprising:

texturing the back surface of the silicon substrate.

17. The method according to claim 11 , wherein the doped region includes a first region that is directly contacted with the metal contact and a second region having a dopant concentration lower than a dopant concentration of the first region.

18. The method according to claim 1 , wherein the silicon substrate and the doped polycrystalline silicon layer have different crystalline structures.

19. A method for manufacturing a solar cell, the method comprising:

providing a silicon substrate;

forming an oxide layer on a first surface of the silicon substrate;

forming a doped polycrystalline silicon layer on the oxide layer;

forming a passivation layer on the doped polycrystalline silicon layer;

printing a metal paste on the passivation layer;

forming a metal contact connected to the doped polycrystalline silicon layer by firing the metal paste to penetrate the passivation layer;

forming a doped region at a second surface of the silicon substrate; and

forming an additional layer on the passivation layer,

wherein only the doped polycrystalline silicon layer among the doped region and the doped polycrystalline silicon layer forms a heterojunction structure with the silicon substrate, and

wherein the passivation layer formed of a first insulating material and the additional layer formed of a second insulating material are sequentially formed on the doped polycrystalline silicon layer, and have a plurality of openings configured to directly connect the metal contact and the doped polycrystalline silicon layer.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 6, 2024
From: SHANGRAO XINYUAN YUEDONG TECHNOLOGY DEVELOPMENT CO. LTD
To: JINGAO SOLAR CO., LTD
Reel/Frame 067329/0132 →
CHANGE OF NAME Recorded Dec 19, 2023
From: SHANGRAO JINKO SOLAR TECHNOLOGY DEVELOPMENT CO., LTD
To: SHANGRAO XINYUAN YUEDONG TECHNOLOGY DEVELOPMENT CO. LTD
Reel/Frame 066078/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 31, 2022
From: CHANG, JAEWON; SHIM, KYUNGJIN; PARK, HYUNJUNG; CHOI, JUNGHOON
To: LG ELECTRONICS INC.
Reel/Frame 061599/0167 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2022
From: LG ELECTRONICS INC.
To: SHANGRAO JINKO SOLAR TECHNOLOGY DEVELOPMENT CO., LTD
Reel/Frame 061572/0487 →