Multi-pixel caching scheme for lossless encoding

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Quick Facts

Patent No.: US 11,653,009
App. No.: 17/509,844
Filed: Oct 25, 2021
Granted: May 16, 2023
Kind: B2
Examiner: JEAN BAPTISTE, JERRY T
Art Unit: 2481
USPC: 375/240.23

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Abstract

Systems and methods are provided for encoding a multi-pixel caching scheme for lossless encoders. The systems and methods can include obtaining a sequence of pixels, determining repeating sub-sequences of the sequence of pixels consisting of a single repeated pixel and non-repeating sub-sequences of the sequence of pixels, responsive to the determination, encoding the repeating sub-sequences using a run-length of the repeated pixel and encoding the non-repeating sub-sequences using a multi-pixel cache, wherein the encoding using a multi-pixel cache comprises, encoding non-repeating sub-sequences stored in the multi-pixel cache as the location of the non-repeating sub-sequences in the multi-pixel cache, and encoding non-repeating sub-sequences not stored in the multi-pixel cache using the value of the pixels in the non-repeating sub-sequences.

Claims (38)

1. A method comprising identifying, by one or more processors, at least one non-repeating sub-sequence of pixels within a sequence of pixels having one or more repeated pixels;

encoding, by the one or more processors, the one or more repeated pixels using a first type of encoding scheme; and

creating, by the one or more processors, a representation of the at least one non-repeating sub-sequence to comprise a first value identifying a cache associated with a number of pixels repeating in the at least one non-repeating sub-sequence and a second value identifying a location with the cache where the at least one non-repeating sub- sequence is stored.

2. The method of claim 1 , wherein the first type of encoding scheme is a run type encoding scheme.

3. The method of claim 1 , determining, by the one or more processors, number of pixels repeating in the at least one non-repeating sub-sequence.

4. The method of claim 1 , further comprising identifying, by the one or more processors, the sequence of pixels for a non-transient region of a display frame.

5. The method of claim 1 , further comprising identifying, by the one or more processors, that the sequence of pixels are to be encoded using lossless encoding.

6. The method of claim 1 , further comprising calculating, by the one or more processors, the second value as a hash value providing an index to the location within the cache where the at least one non-repeating sub-sequence is stored.

7. The method of claim 1 , further comprising determining, by the one or more processors, that at least a second non-repeating sub-sequence within the sequence is not stored in one or more caches.

8. The method of claim 7 , further comprising creating, the one or more processors, a second representation of the second non-repeating sub-sequence to comprise a byte to signal a cache-miss for the second non-repeating sub-sequence.

9. A system comprising one or more processors, coupled to memory and configured to:

identify at least one non-repeating sub-sequence of pixels within a sequence of pixels having one or more repeated pixels;

encode the one or more repeated pixels using a first type of encoding scheme; and create a representation of the at least one non-repeating sub-sequence to comprise a first value identifying a cache associated with a number of pixels repeating in the at least one non-repeating sub-sequence and a second value identifying a location with the cache where the at least one non-repeating subsequence is stored.

10. The system of claim 9 , wherein the first type of encoding scheme is a run type encoding scheme.

11. The system of claim 9 , wherein the one or more processors are further configured to determine the number of pixels repeating in the at least one non-repeating sub-sequence.

12. The system of claim 9 , wherein the one or more processors are further configured to identify the sequence of pixels for a non-transient region of a display frame.

13. The system of claim 9 , wherein the one or more processors are further configured to identify that the sequence of pixels are to be encoded using lossless encoding.

14. The system of claim 9 , wherein the one or more processors are further configured to calculate the second value as a hash value providing an index to the location within the cache where the at least one non-repeating sub-sequence is stored.

15. The system of claim 9 , wherein the one or more processors are further configured to determine that at least a second non-repeating sub-sequence within the sequence is not stored in one or more caches.

16. The system of claim 15 , wherein the one or more processors are further configured to create a second representation of the second non-repeating sub-sequence to comprise a byte to signal a cache-miss for the second non-repeating sub-sequence.

17. A system comprising one or more processors, coupled to memory and configured to:

identify at least one non-repeating sub-sequence of pixels within a sequence of pixels having one or more repeated pixels;

encode the one or more repeated pixels using a first type of encoding scheme; and create a representation of the at least one non-repeating subsequence to comprise a first value identifying a cache associated with a number of pixels repeating in the at least one non-repeating sub-sequence and a second value identifying a location with the cache where the at least one non-repeating sub-sequence is stored.

18. The system of claim 9 , wherein the first type of encoding scheme is a run type encoding scheme.

19. The system of claim 9 , wherein the one or more processors are further configured to determine the number of pixels repeating in the at least one non-repeating sub-sequence.

20. The system of claim 9 , wherein the one or more processors are further configured to identify the sequence of pixels for a non-transient region of a display frame.

21. The system of claim 9 , wherein the one or more processors are further configured to identify that the sequence of pixels are to be encoded using lossless encoding.

22. The system of claim 9 , wherein the one or more processors are further configured to calculate the second value as a hash value providing an index to the location within the cache where the at least one non-repeating sub-sequence is stored.

23. The system of claim 9 , wherein the one or more processors are further configured to determine that at least a second non-repeating sub-sequence within the sequence is not stored in any cache.

24. The system of claim 15 , wherein the one or more processors are further configured to create a second representation of the second non-repeating sub-sequence to comprise a byte to signal a cache-miss for the second non-repeating sub-sequence.

25. A non-transitory computer-readable medium storing instructions that, when executed by one or more processors, cause the one or more processors to

identify at least one non-repeating sub-sequence of pixels within a sequence of pixels having one or more repeated pixels;

encode the one or more repeated pixels using a first type of encoding scheme; and

create a representation of the at least one non-repeating subsequence to comprise a first value identifying a cache associated with a number of pixels repeating in the at least one non-repeating sub-sequence and a second value identifying a location with the cache where the at least one non-repeating sub-sequence is stored.

26. The non-transitory computer-readable medium of claim 25 , further comprising instructions to configured to cause the one or more processors to determine the number of pixels repeating in the at least one non-repeating sub-sequence.

27. The non-transitory computer-readable medium of claim 25 , further comprising instructions to configured to cause the one or more processors to identify the sequence of pixels for a non-transient region of a display frame.

28. The non-transitory computer-readable medium of claim 25 , further comprising instructions to configured to cause the one or more processors to determine that at least a second non-repeating sub-sequence within the sequence is not stored in one or more caches.

29. The non-transitory computer-readable medium of claim 25 , further comprising instructions to configured to cause the one or more processors to create a second representation of the second non-repeating sub-sequence to comprise a byte to signal a cache-miss for the second non-repeating sub-sequence.