Silicon photonic interposer with two metal redistribution layers

1. A method for fabricating a silicon integrated circuit, the method comprising:

fabricating a first intermediate product, comprising:

a silicon substrate,

a first conductive layer on the silicon substrate, and

a dielectric layer on the first conductive layer;

etching a first opening and a second opening, into the dielectric layer, onto the first conductive layer;

forming a second conductive layer on the dielectric layer and on the first conductive layer in the first opening and in the second opening; and

removing a portion of the second conductive layer in a region including the second opening and a region surrounding the second opening.

2. The method of claim 1 , further comprising forming a wire bond pad on the first conductive layer in the second opening.

3. The method of claim 1 , further comprising:

forming an under bump metallization capture pad on:

the first conductive layer in the second opening, and

a region surrounding the second opening; and

removing a remainder of the second conductive layer in a region around the under bump metallization capture pad.

4. The method of claim 3 , wherein the under bump metallization capture pad comprises:

a layer of nickel, and

a layer of gold on the layer of nickel.

5. The method of claim 1 , wherein the first conductive layer is composed of a material selected from the group consisting of aluminum, copper, gold, and alloys and combinations thereof.

6. The method of claim 1 , wherein the second conductive layer comprises a layer of a material selected from the group consisting of gold, copper, aluminum, and alloys and combinations thereof.

7. The method of claim 6 , wherein the second conductive layer further comprises a layer of material selected from the group consisting of titanium, tungsten, tantalum, and alloys and combinations thereof.

8. The method of claim 1 , wherein the dielectric layer is composed of a material selected from the group consisting of silicon dioxide, silicon nitride, benzocyclobutene, polyimides, and combinations thereof.

9. A silicon integrated circuit fabricated using the method of claim 1 , the silicon integrated circuit comprising:

a first conductive trace, on a top surface of the silicon integrated circuit;

the dielectric layer, wherein the dielectric layer is on the first conductive trace; and

a second conductive trace, on the dielectric layer, connected to the first conductive trace through a first via.

10. The silicon integrated circuit of claim 9 , further comprising an under bump metallization capture pad, on, and connected to the first conductive trace through, a second via.

11. The silicon integrated circuit of claim 10 , wherein the under bump metallization capture pad comprises:

a layer of nickel, and

a layer of gold on the layer of nickel.

12. The silicon integrated circuit of claim 9 , further comprising a wire bond pad, on, and connected to the first conductive trace through, a second via.

13. The silicon integrated circuit of claim 9 , wherein the first conductive trace is composed of a material selected from the group consisting of gold, aluminum, copper, and alloys and combinations thereof.

14. The silicon integrated circuit of claim 9 , wherein the second conductive trace is composed of a material selected from the group consisting of gold, aluminum, copper, titanium, tungsten, tantalum, and alloys and combinations thereof.

15. The silicon integrated circuit of claim 14 , wherein the second conductive trace further comprises a layer of titanium tungsten.

16. The silicon integrated circuit of claim 9 , wherein the dielectric layer is composed of a material selected from the group consisting of silicon dioxide, silicon nitride, benzocyclobutene, polyimides, and combinations thereof.

17. The silicon integrated circuit of claim 9 , wherein the dielectric layer is composed of silicon nitride.