IP Library Granted Patent US 11,924,312
Granted Patent B2
US 11,924,312 · App. 17/030,439 · Granted Mar 5, 2024

EtherCAT controllers

Inventors: William Mahany (West Islip, NY); Ian Saturley (Warwickshire, GB); Lakshmi Narasimhan (Chennai, IN); Riyas Kattukandan (Kerala, IN); Ramya Kuppusamy (Karnataka, IN); Robert Zakowicz (Chandler, AZ)
Assignee: Microchip Technology Incorporated
H04L69/22G06F9/4418H04J3/0658H04L12/10
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Quick Facts
Patent No.
US 11,924,312
App. No.
17/030,439
Filed
Sep 24, 2020
Granted
Mar 5, 2024
Kind
B2
Art Unit
2462
USPC
370/392
Abstract

An EtherCAT device includes a communications circuit and a wakeup circuit. The wakeup circuit is configured to determine a condition in which to send data to an EtherCAT master node. The wakeup circuit, based on such a condition, is configured to generate a wakeup packet. The communications circuit may be configured to receive an EtherCAT frame originating from the EtherCAT master node. The communications circuit may be configured to populate the EtherCAT frame with the data to be sent to the EtherCAT master node. The communications circuit may be configured to send the EtherCAT frame to the EtherCAT master device.

Claims (38)

1. An EtherCAT device configured to be included in an EtherCAT network with an EtherCAT master node, the EtherCAT device comprising:

a processor configured to operate in a sleep mode and in a normal operating mode; and

a network interface card (NIC) including circuitry configured to:

receive incoming EtherCAT packets from the EtherCAT network originally issued by the EtherCAT master node; and

while the processor is in the sleep mode:

parse the incoming EtherCAT packets;

determine whether a given incoming EtherCAT packet is a wake-on-LAN (WoL) packet by:

a determination that the given incoming EtherCAT packet includes an address of another EtherCAT device;

a determination that the given incoming EtherCAT packet includes a predetermined value within a payload;

a determination that the given incoming EtherCAT packet includes an address of the EtherCAT device;

a determination that the given incoming EtherCAT packet includes an address of another EtherCAT device; or

a determination that the given incoming EtherCAT packet includes an address of the EtherCAT master node;

based on a determination that the given incoming EtherCAT packet is a WoL packet, generate a wake signal to the processor; and

forward the given incoming EtherCAT packet to another node in the EtherCAT network.

2. The EtherCAT device of claim 1 , wherein the determination whether the given incoming EtherCAT packet is a WoL packet is based on a determination that the given incoming EtherCAT packet is a broadcast packet.

3. The EtherCAT device of claim 1 , wherein the determination whether the given incoming EtherCAT packet is a WoL packet is based on a determination that the given incoming EtherCAT packet includes a predetermined value within a payload.

4. The EtherCAT device of claim 1 , wherein the determination whether the given incoming EtherCAT packet is a WoL packet is based on a determination that the given incoming EtherCAT packet includes an address of the EtherCAT device.

5. The EtherCAT device of claim 1 , wherein the determination whether the given incoming EtherCAT packet is a WoL packet is based on a determination that the given incoming EtherCAT packet includes an address of another EtherCAT device.

6. The EtherCAT device of claim 1 , wherein the determination whether the given incoming EtherCAT packet is a WoL packet is based on a determination that the given incoming EtherCAT packet includes an address of the EtherCAT master node.

7. A method, comprising:

operating a processor configured to operate in a sleep mode and in a normal operating mode; and

with a network interface card (NIC):

receiving incoming EtherCAT packets from an EtherCAT network originally issued by an EtherCAT master node; and

while the processor is in the sleep mode:

parsing the incoming EtherCAT packets;

determining whether a given incoming EtherCAT packet is a wake-on-LAN (WoL) packet by determining:

 that the given incoming EtherCAT packet is a broadcast packet;

 that the given incoming EtherCAT packet includes a predetermined value within a payload;

 that the given incoming EtherCAT packet includes an address of the EtherCAT device;

 that the given incoming EtherCAT packet includes an address of another EtherCAT device; or

 that the given incoming EtherCAT packet includes an address of the EtherCAT master node;

based on a determination that the given incoming EtherCAT packet is a WoL packet, generating a wake signal to the processor; and

forwarding the given incoming EtherCAT packet to another node in the EtherCAT network.

8. The method of claim 7 , wherein the determination of whether the given incoming EtherCAT packet is a WoL packet is made by determining that the given incoming EtherCAT packet is a broadcast packet.

9. The method of claim 7 , wherein the determination of whether the given incoming EtherCAT packet is a WoL packet is made by determining that the given incoming EtherCAT packet includes a predetermined value within a payload.

10. The method of claim 7 , wherein the determination of whether the given incoming EtherCAT packet is a WoL packet is made by determining that the given incoming EtherCAT packet includes an address of the EtherCAT device.

11. The method of claim 7 , wherein the determination of whether the given incoming EtherCAT packet is a WoL packet is made by determining that the given incoming EtherCAT packet includes an address of another EtherCAT device.

12. The method of claim 7 , wherein the determination of whether the given incoming EtherCAT packet is a WoL packet is made by determining that the given incoming EtherCAT packet includes an address of the EtherCAT master node.