IP Library Granted Patent US 12,074,692
Granted Patent B2
US 12,074,692 · App. 18/115,566 · Granted Aug 27, 2024

Method of measuring timing holdover performance in an R-PHY system

Inventor: Yair Neugeboren (Netanya, IL)
Assignee: ARRIS Enterprises LLC
H04J3/0632H04J3/0667
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Quick Facts
Patent No.
US 12,074,692
App. No.
18/115,566
Filed
Feb 28, 2023
Granted
Aug 27, 2024
Kind
B2
Art Unit
2461
USPC
370/516
Abstract

Systems and methods for measuring the amount of drift of a clock in a remote device relative to a clock in a core, both in a distributed access architecture, by measuring the change in fullness of a dejitter buffer in the remote device that holds data provided from the core.

Claims (13)

1. A remote device in a distributed access architecture of a communications network, the remote device operatively connected to a core providing data to the remote device, the remote device including a dejitter buffer and a processor configured to measure sequential values, each value representing an instantaneous fullness state of the dejitter buffer, and use the values to determine a magnitude of phase drift of a first clock of the remote device relative to a second clock of the core;

the remote device including a low pass filter that filters the sequential values; and

where the output of the low pass filter is used to determine a sequence of fractional frequency offset values.

2. The remote device of claim 1 where the processor accumulates the sequence of fractional frequency offset values to provide an accumulated value and compares the accumulated value to a threshold.

3. The remote device of claim 2 where the remote device provides an alert based on the comparison.

4. A method implemented by a processor of a network device in a distributed access architecture, the method comprising:

measuring sequential values representing a fullness state of a dejitter buffer of the network device, the network device having a first clock;

using the sequential values to determine a magnitude of phase drift of the first clock relative to a second clock associated with a second device providing data to the dejitter buffer;

applying a low pass filter to the sequential values;

where the output of the low pass filter is used to determine a sequence of fractional frequency offset values.

5. The method of claim 4 further comprising accumulating the sequence of fractional frequency offset values to provide an accumulated value.

6. The method of claim 5 further comprising comparing the accumulated value to a threshold.

7. The method of claim 6 further comprising providing an alert based on the comparison.