Memory (NVM) devices for use with recurrent neural networks
Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may include a Neural Turning Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, a data storage device (DSD) that controls the NVM array includes both a data storage controller and a separate NTM controller. The separate NTM controller accesses the NTM matrix of the NVM array directly while bypassing flash translation layer (FTL) components of the data storage controller. Additionally, various majority wins error detection and correction procedures are described, as well as various disparity count-based procedures.
1. A data storage device, comprising:
a non-volatile memory (NVM) array; and
a controller coupled to the NVM array and having one or more processors configured to:
read scrambled neural network data from the NVM array;
determine a disparity between a count of binary ones and a count of binary zeroes in the scrambled neural network data;
determine whether the disparity exceeds a disparity threshold;
descramble the scrambled neural network data read from the NVM array, in response to a determination that the disparity does not exceed the disparity threshold; and
generate an indication of an error, in response to a determination that the disparity exceeds the disparity threshold.
2. The data storage device of claim 1 , wherein the one or more processors are further configured to process the descrambled neural network data using a machine learning procedure.
3. The data storage device of claim 1 , wherein the one or more processors are further configured to apply an error mitigation procedure to the NVM array, in response to the indication of the error.
4. The data storage device of claim 3 , wherein the one or more processors are further configured to apply a read threshold calibration error mitigation procedure to the NVM array, in response to the indication of the error.
5. The data storage device of claim 1 , wherein the one or more processors are further configured to maintain a running total in the disparity over time.
6. The data storage device of claim 5 , wherein the one or more processors are further configured to determine whether the disparity exceeds the disparity threshold by being further configured to determine whether the running total exceeds the disparity threshold.
7. The data storage device of claim 5 , wherein the one or more processors are further configured to:
store a plurality of disparity counts over time, each disparity count representative of the running total of the disparity counts at a different point in time;
detect a trend in the disparity counts over time indicative of data retention degradation; and
determine a cause of the data retention degradation based on the trend.
8. The data storage device of claim 7 , wherein the one or more processors are further configured to determine the cause of the data retention degradation based on the trend by being further configured to determine that (a) a trend toward a greater disparity in binary ones over binary zeroes is indicative of increasing read thresholds and (b) a trend toward a greater disparity in binary zeroes over binary ones is indicative of decreasing read thresholds.
9. The data storage device of claim 1 , wherein the one or more processors are further configured to:
scramble neural network data received from a host using at least one of an error correction code (ECC) component or a data scrambler; and
store the scrambled neural network data in the NVM array.
10. The data storage device of claim 1 , wherein the one or more processors are further configured to compensate for an intrinsic bias in the scrambled neural network data while determining the disparity.
11. A method for use with a data storage device that includes a non-volatile memory (NVM) array, the method comprising:
reading scrambled neural network data from the NVM array;
determining a disparity between a count of binary ones and a count of binary zeroes in the scrambled neural network data;
determining whether the disparity exceeds a disparity threshold;
descrambling the scrambled neural network data read from the NVM array, in response to a determination that the disparity does not exceed the disparity threshold; and
generating an indication of an error, in response to a determination that the disparity exceeds the disparity threshold.
12. The method of claim 11 , further comprising processing the descrambled neural network data using a machine learning procedure.
13. The method of claim 11 , further comprising applying an error mitigation procedure to the NVM array, in response to the indication of the error.
14. The method of claim 13 , further comprising applying a read threshold calibration error mitigation procedure to the NVM array, in response to the indication of the error.
15. The method of claim 11 , further comprising maintaining a running total in the disparity over time.
16. The method of claim 15 , further comprising determining whether the disparity exceeds the disparity threshold by determining whether the running total exceeds the disparity threshold.
17. The method of claim 15 , further comprising:
storing a plurality of disparity counts over time, each disparity count representative of the running total of the disparity counts at a different point in time;
detecting a trend in the disparity counts over time indicative of data retention degradation; and
determining a cause of the data retention degradation based on the trend.
18. The method of claim 17 , wherein determining the cause of the data retention degradation based on the trend comprises determining that (a) a trend toward a greater disparity in binary ones over binary zeroes is indicative of increasing read thresholds and (b) a trend toward a greater disparity in binary zeroes over binary ones is indicative of decreasing read thresholds.
19. The method of claim 11 , further comprising:
scrambling neural network data received from a host using at least one of an error correction code (ECC) component or a data scrambler; and
storing the scrambled neural network data in the NVM array.
20. An apparatus for use with a data storage device that includes a non-volatile memory (NVM) array, the apparatus comprising:
means for reading scrambled neural network data from the NVM array;
means for determining a disparity between a count of binary ones and a count of binary zeroes in the scrambled neural network data;
means for determining whether the disparity exceeds a disparity threshold;
means for descrambling the scrambled neural network data read from the NVM array, in response to a determination that the disparity does not exceed the disparity threshold; and
means for generating an indication of an error, in response to a determination that the disparity exceeds the disparity threshold.