Data storage device and method for accommodating data of a third-party system
A data storage device and method are provided for accommodating data of a third-party system. In one embodiment, a data storage device is provided comprising a memory and one or more processors. The one or more processors, individually or in combination, are configured to: receive data from a graphics processing unit (GPU) of a host; segregate the data; determine whether the host is pre-approved for a capacity condition; and in response to determining that the host is pre-approved for the capacity condition: associate the segregated data per a pre-approved destination; and consolidate logical-to-physical address entry updates into a logical-to-physical address data structure. Other embodiments are provided.
1 . A data storage device comprising:
a memory; and
one or more processors, individually or in combination, configured to:
receive data and a logical address directly from a graphics processing unit (GPU) of a host as opposed to indirectly through a central processing unit (CPU) of the host;
store the data in a location of the memory configured to store only data received from the GPU as opposed to data received from the CPU;
store an entry in a secondary logical-to-physical address data structure to reflect that the data is stored in the location in the memory, wherein the secondary logical-to-physical address data structure stores only entries for the location in the memory as opposed to other locations in the memory that store data received from the CPU;
determine whether the data is pre-approved for a capacity condition;
in response to determining that the data is not pre-approved for the capacity condition:
discard the entry in the secondary logical-to-physical address data structure; and
perform garbage collection only in the location in the memory as opposed to the other locations in the memory; and
in response to determining that the data is pre-approved for the capacity condition: merge the secondary logical-to-physical address data structure into a primary logical-to-physical address data structure that stores entries for the other locations in the memory.
2 . The data storage device of claim 1 , wherein the data is received with a GPU identifier.
3 . The data storage device of claim 1 , wherein the logical address is part of a logical block address (LBA) range associated with the GPU.
4 . The data storage device of claim 1 , wherein the one or more processors, individually or in combination, are further configured to:
move the data to capacity blocks.
5 . The data storage device of claim 1 , wherein the one or more processors, individually or in combination, are further configured to:
monitor input-output data of the GPU and at least one additional GPU; and
route the input-output data based on an instruction from the host.
6 . The data storage device of claim 1 , wherein the one or more processors, individually or in combination, are further configured to:
monitor input-output data of the GPU and at least one additional GPU; and
generate parity for the input-output data based on an instruction from the host.
7 . The data storage device of claim 1 , wherein the one or more processors, individually or in combination, are further configured to:
monitor input-output data of the GPU and at least one additional GPU; and
perform quality-of-service biasing of the input-output data based on an instruction from the host.
8 . The data storage device of claim 1 , wherein the memory comprises a three-dimensional memory.
9 . A method comprising:
performing in a data storage device comprising a memory:
receiving data and a logical address directly from a graphics processing unit (GPU) of a host as opposed to indirectly through a central processing unit (CPU) of the host;
storing the data in a location of the memory configured to store only data received from the GPU as opposed to data received from the CPU;
storing an entry in a secondary logical-to-physical address data structure to reflect that the data is stored in the location in the memory, wherein the secondary logical-to-physical address data structure stores only entries for the location in the memory as opposed to other locations in the memory that store data received from the CPU;
determining whether the host is pre-approved for a capacity condition;
in response to determining that the host is pre-approved for the capacity condition:
discarding the entry in the secondary logical-to-physical address data structure; and
performing garbage collection only in the location in the memory as opposed to the other locations in the memory; and
in response to determining that the data is pre-approved for the capacity condition: merging the secondary logical-to-physical address data structure into a primary logical-to-physical address data structure that stores entries for the other locations in the memory.
10 . The method of claim 9 , wherein the data is received with a GPU identifier.
11 . The method of claim 9 , wherein the logical address is part of a logical block address (LBA) range associated with the GPU.
12 . The method of claim 9 , further comprising:
moving the data to capacity blocks.
13 . The method of claim 9 , further comprising:
monitoring input-output data of the GPU and at least one additional GPU; and
routing the input-output data based on an instruction from the host.
14 . The method of claim 9 , further comprising:
monitoring input-output data of the GPU and at least one additional GPU; and
generating parity for the input-output data based on an instruction from the host.
15 . The method of claim 9 , further comprising:
monitoring input-output data of the GPU and at least one additional GPU; and
performing quality-of-service biasing of the input-output data based on an instruction from the host.
16 . A data storage device comprising:
a memory; and
means for:
receiving data and a logical address directly from a graphics processing unit (GPU) of a host as opposed to indirectly through a central processing unit (CPU) of the host;
storing the data in a location of the memory configured to store only data received from the GPU as opposed to data received from the CPU;
storing an entry in a secondary logical-to-physical address data structure to reflect that the data is stored in the location in the memory, wherein the secondary logical-to-physical address data structure stores only entries for the location in the memory as opposed to other locations in the memory that store data received from the CPU;
determining whether the host is pre-approved for a capacity condition;
in response to determining that the host is pre-approved for the capacity condition:
discarding the entry in the secondary logical-to-physical address data structure; and
performing garbage collection only in the location in the memory as opposed to the other locations in the memory; and
in response to determining that the host is pre-approved for the capacity condition: merging the secondary logical-to-physical address data structure into a primary logical-to-physical address data structure that stores entries for the other locations in the memory.