Read for non-volatile memory with reduced current levels
Technology is disclosed herein for a storage system and method for reducing current levels while maintaining performance during a sensing operation. While initially ramping up and subsequently discharging the bias level on a selected word line, a selected bit line is set to float to thereby reduce current levels. The word line is then biased at a read voltage for a data state and, after being allowed to settle, the selected memory cell is sensed by determining the current though the selected memory cell. To improve performance, when the word line is biased at the read voltage, a voltage spike or kick is applied to selected bit line, after which it is biased at bit line sensing voltage while the selected word line settles and sensing occurs.
1 . A non-transitory non-volatile memory apparatus, comprising:
a control circuit configured to connect to a memory structure comprising a plurality of memory cells each connected along a corresponding word line and to a corresponding bit line, where, to read a selected memory cell connected along a selected word line and to a selected bit line, the control circuit is configured to:
bias the selected word line to a first sensing voltage;
while biased at the first sensing voltage, allow the selected word line to settle;
with the selected word line biased at the first sensing voltage and subsequent to being allowed to settle, determine a first state of the selected memory cell based on an amount of current flowing from the selected bit line through the selected memory cell;
prior to biasing the selected word line to the first sensing voltage, bias the selected word line to an initial voltage level higher than the first sensing voltage and subsequently allowing the selected word line to discharge from the initial voltage level towards the first sensing voltage;
while the selected word line is ramping towards the initial voltage and subsequently discharging toward the first sensing voltage, set the selected bit line to float;
concurrently with initially biasing the selected word line to the first sensing voltage, applying a voltage spike to the selected bit line;
while the selected word line is settling, allow the corresponding bit line to discharge from the voltage spike to a selected bit line sensing voltage; and
while determining the first state of the selected memory cell, bias the selected bit line at the selected bit line sensing voltage.
2 . The non-transitory non-volatile memory apparatus of claim 1 , wherein at least a portion of the control circuit is formed on a control die, the non-volatile memory apparatus further comprising:
a memory die including the memory structure, the memory die separate from and bonded to the control die.
3 . The non-transitory non-volatile memory apparatus of claim 1 , wherein the control circuit comprises:
a sense amplifier circuit configured to bias the selected bit line; and
a bit line switch through which the sense amplifier circuit is connectable to the selected bit line.
4 . The non-transitory non-volatile memory apparatus of claim 3 , wherein:
to set the selected bit line to float, the control circuit is configured to turn the bit line switch off; and
to bias the selected bit line to the bit line sensing voltage, the control circuit is configured to turn the bit line switch on.
5 . The non-transitory non-volatile memory apparatus of claim 1 , wherein the memory structure has a NAND architecture and the control circuit is further configured to:
concurrently with biasing the selected word line to an initial voltage level higher than the first sensing voltage, biasing unselected word lines of the memory structure to a read pass voltage.
6 . The non-transitory non-volatile memory apparatus of claim 5 , further comprising:
the memory structure, wherein the memory structure has a three-dimensional NAND architecture.
7 . The non-transitory non-volatile memory apparatus of claim 1 , wherein to bias the selected word line to an initial voltage level higher than the first sensing voltage, the control circuit is further configured to:
bias the selected word line to an intermediate voltage level between ground and the initial voltage level; and
subsequent to biasing the selected word line to the intermediate voltage level, biasing the selected word line to the initial voltage level.
8 . The non-transitory non-volatile memory apparatus of claim 1 , wherein, subsequent to determining the first state of the selected memory cell, the control circuit is further configured to:
bias the selected word line to a second sensing voltage;
while the selected word line is biased at the second sensing voltage, allow the selected word line to settle;
while biased at the second sensing voltage and subsequent to being allowed to settle, determine a second state of the selected memory cell based on an amount of current flowing from the selected bit line through the selected memory cell;
prior to biasing the selected word line to the second sensing voltage, allowing the selected word line to discharge towards the second sensing voltage;
while the selected word line is discharging toward the second sensing voltage, set the selected bit line to float;
concurrently with initially biasing the selected word line to the second sensing voltage, applying a voltage spike to the selected bit line; and
while the selected word line is settling, allow the selected bit line to discharge to a selected bit line sensing voltage.
9 . The non-transitory non-volatile memory apparatus of claim 8 , wherein the memory cells are multi-level memory cells configured to store data in a multipage format, and wherein the first sensing voltage and the second sensing voltage are configured to determine a data value of the selected memory cell for a page of the multipage format.
10 . The non-transitory non-volatile memory apparatus of claim 9 , wherein the control circuit is further configured to:
prior to reading the selected memory cell, programing the data value to the selected memory cell.
11 . A method, comprising:
selecting a non-volatile memory cell of a memory structure comprising a plurality of non-volatile memory cells for a sensing operation;
biasing a first word line connected to a selected memory cell to an initial voltage level and subsequently allowing the first word line to discharge from the initial voltage level toward a voltage level below a first sensing voltage, the initial voltage level being higher than the first sensing voltage;
while the first word line ramps to the initial voltage level and subsequently discharges, setting a first bit line connected to the selected memory cell to float;
subsequent to the first word line discharging to the voltage level below the first sensing voltage, biasing the first word line at the first sensing voltage;
while the first word line ramps from the voltage level below the first sensing voltage to the first sensing voltage in respect the biasing of the first word line to the first sensing voltage, applying a voltage spike to the first bit line;
while biasing the first word line at the first sensing voltage, subsequent to the first word line ramping from the voltage level below the first sensing voltage to the first sensing voltage, allowing the first word line to settle;
while the first word line is biased at the first sensing voltage and subsequent to being allowed to settle, determining a first state of the selected memory cell based on an amount of current flowing from the first bit line through the selected memory cell;
while the first word line is settling, allowing the first bit line to discharge from the voltage spike to a selected bit line sensing voltage; and
while determining the first state of the selected memory cell, biasing the first bit line at the selected bit line sensing voltage.
12 . The method of claim 11 , wherein biasing the first bit line at the selected bit line sensing voltage includes:
biasing the selected first bit line at the selected bit line sensing voltage by a sense amplifier circuit.
13 . The method of claim 12 , wherein the sense amplifier circuit is connected to the first bit line though a bit line switch, and
wherein setting the first bit line connected to the selected memory cell to float includes setting the bit line switch to be off.
14 . The method of claim 11 , wherein the memory structure has a NAND architecture and the method further comprises:
concurrently with biasing the first word line to an initial voltage level higher than the first sensing voltage, biasing unselected word lines of the memory structure to a read pass voltage.
15 . The method of claim 11 , biasing the first word line to an initial voltage level higher than the first sensing voltage comprises:
biasing the first word line to an intermediate voltage level between ground and the initial voltage level; and
subsequent to biasing the first word line to the intermediate voltage level, biasing the first word line to the initial voltage level.
16 . The method of claim 11 , further comprising subsequent to determining the first state of the selected memory cell:
biasing the first word line to a second sensing voltage;
while biased at the second sensing voltage, allowing the first word line to settle;
while the first word line biased at the second sensing voltage and subsequent to being allowed to settle, determining a second state of the selected memory cell based on an amount of current flowing from the first bit line through the selected memory cell;
prior to biasing the first word line to the second sensing voltage, allowing the first word line to discharge towards the second sensing voltage;
while the first word line is discharging toward the second sensing voltage, setting the first bit line to float;
concurrently with initially biasing the first word line to the second sensing voltage, applying a voltage spike to the first bit line; and
while the first word line is settling, allowing the first bit line to discharge to a selected bit line sensing voltage.
17 . The method of claim 16 , wherein the memory cells are multi-level memory cells configured to store data in a multipage format, and wherein the first sensing voltage and the second sensing voltage are configured to determine a data value of the selected memory cell for a page of the multipage format.
18 . A non-transitory non-volatile memory apparatus, comprising:
an array of non-volatile memory cells each connected along a corresponding word line and a corresponding bit line; and
one or more control circuits, comprising:
word line driver circuitry configured to:
bias a word line connected to a selected memory cell to an initial voltage level and subsequently allow the word line connected to a selected memory cell to discharge from the initial voltage level toward a voltage level below a first sensing voltage, the initial voltage level being higher than the first sensing voltage;
subsequent to the word line connected to the selected memory cell discharging to the voltage level below the first sensing voltage, bias the word line connected to the selected memory cell the first sensing voltage; and
while biasing the word line connected to a selected memory cell at the first sensing voltage and subsequent to the word line connected to the selected memory cell ramping from the voltage level below the first sensing voltage to the first sensing voltage, allowing the word line connected to the selected memory cell to settle; and
bit line driver circuitry configured to:
while the word line connected to the selected memory cell ramps to the initial voltage level and subsequently discharges, set a bit line connected to the selected memory cell to float;
while the word line connected to the selected memory cell ramps from the voltage level below the first sensing voltage to the first sensing voltage in respect the biasing of the word line connected to the selected memory cell to the first sensing voltage, apply a voltage spike to the bit line connected to the selected memory cell; and
subsequent to applying the voltage spike to the bit line connected to the selected memory cell, bias the bit line connected to the selected memory cell at a selected bit line sensing voltage,
the control circuit configured to:
while the word line connected to the selected memory cell is biased at the first sensing voltage and subsequent to being allowed to settle and while the bit line connected to the selected memory cell is biased at the selected bit line sensing voltage, determine a state of the selected memory cell based on an amount of current flowing from the bit line connected to the selected memory cell through the selected memory cell.
19 . The non-transitory non-volatile memory apparatus of claim 18 , wherein the one or more control circuits further comprise:
a sense amplifier circuit; and
a bit line switch connecting the sense amplifier to the bit line connected to the selected memory cell,
wherein, to set the bit line connected to the selected memory cell to float, the one or more control circuits are configured to turn the bit line switch off,
wherein to bias the bit line connected to the selected memory cell at the selected bit line sensing voltage the one or more control circuit are configured to turn the bit line select switch on and bias the bit line connected to the selected memory cell by the sense amplifier circuit, and
wherein the sense amplifier circuit is configured to determine the state of the selected memory cell based on an amount of current flowing from the bit line connected to the selected memory cell through the selected memory cell.
20 . The non-transitory non-volatile memory apparatus of claim 18 , wherein the array of non-volatile memory cells has a NAND structure and the word line driver circuitry is further configured to:
concurrently with biasing the word line connected to the selected memory cell to an initial voltage level higher than the first sensing voltage, biasing unselected word lines of the array of non-volatile memory cells to a read pass voltage.