Vacancy-rich silicon for use with a gallium nitride epitaxial layer
View Patent ↗A manufacturing process is described to evaluate and select raw semiconductor wafers in preparation for epitaxial layer formation. The manufacturing process first produces a single crystal ingot during which a seed pulling velocity and temperature gradient are closely controlled. The resulting ingot is vacancy-rich with relatively few self-interstitial defects. Selected wafers can advance to a high-temperature nitridation annealing operation that further reduces the number of interstitials while increasing the vacancies. Substrates characterized by a high vacancy density can then be used to optimize an epitaxial layer deposition process.
1 . A method, comprising:
forming a crystal ingot from a crystal melt by pulling a solid crystal from the crystal melt at a pulling velocity V, the crystal ingot having a central region and an outer radius;
while forming the crystal ingot, adjusting a ratio of the pulling velocity V to an axial temperature gradient G(V/G), wherein adjusting the ratio V/G adjusts characteristics of self-interstitial defects that form at the outer radius and vacancy defects that form in the central region;
selecting a vacancy-rich region of the crystal ingot, wherein the vacancy-rich region comprises an oxidation induced stacking fault ring;
cutting vacancy-rich semiconductor wafers from the vacancy-rich region of the crystal ingot; and
removing the oxidation induced stacking fault ring in the vacancy-rich semiconductor wafers.
2 . The method of claim 1 , wherein forming the crystal ingot comprises forming a silicon crystal ingot, and wherein cutting the vacancy-rich semiconductor wafers comprises cutting vacancy-rich silicon wafers.
3 . The method of claim 1 , wherein the characteristics of the self-interstitial and vacancy defects comprise one or more of a number of the self-interstitial and vacancy defects, a density of the self-interstitial and vacancy defects, and a distribution of the self-interstitial and vacancy defects.
4 . The method of claim 1 , wherein pulling the solid crystal comprises pulling a solid crystal that is suitable for manufacturing semiconductor devices comprising one or more of silicon, germanium, compound semiconductors, and alloy semiconductors.
5 . The method of claim 1 , wherein the ratio V/G is within a range of about 0.00155 cm 2 /min ° K to about 0.0020 cm 2 /min ° K.
6 . A method, comprising:
identifying vacancy-rich semiconductor wafers from among a group of semiconductor wafers, wherein a peripheral region of each of the vacancy-rich semiconductor wafers comprises an oxidation induced stacking fault ring;
removing the oxidation induced stacking fault ring by applying an annealing process to the vacancy-rich semiconductor wafers;
performing a nitridation operation that exposes the vacancy-rich semiconductor wafers to a nitrogen gas; and
epitaxially growing gallium nitride on the annealed vacancy-rich semiconductor wafers.
7 . The method of claim 6 , wherein applying the annealing process comprises performing a thermal operation that exposes the vacancy-rich semiconductor wafers to temperatures greater than about 1200° C.
8 . The method of claim 7 , wherein a high-temperature phase of the thermal operation has a duration between about 60 seconds and 200 seconds.
9 . The method of claim 6 , wherein a gas pressure of the nitridation operation is between about 0.9 atm and about 1.1 atm.
10 . The method of claim 6 , further comprising, after the annealing process, evaluating a thermal conductivity of the vacancy-rich semiconductor wafers.
11 . The method of claim 10 wherein evaluating the thermal conductivity of the vacancy-rich silicon wafers comprises making a thermal map of an annealed wafer for comparison with a standard for cross-wafer uniformity of thermal conductivity.
12 . The method of claim 6 , further comprising, after the annealing process, evaluating a vacancy density of the vacancy-rich wafers.
13 . The method of claim 6 , wherein identifying the vacancy-rich semiconductor wafers comprises evaluating a vacancy density of the group of semiconductor wafers by creating a wafer map showing a profile of oxidation induced stacking faults.
14 . The method of claim 13 , wherein identifying the vacancy-rich semiconductor wafers comprises a quality control operation in which features of vacancy-rich wafers are enhanced by imaging for automated detection.
15 . The method of claim 13 , wherein identifying the vacancy-rich semiconductor wafers comprises a quality control operation in which features of vacancy-rich wafers are enhanced by wet chemical processing for automated detection.
16 . The method of claim 6 , wherein epitaxially growing the gallium nitride on the annealed vacancy-rich semiconductor wafers comprises epitaxially growing the gallium nitride using a metal-organic chemical vapor deposition process.
17 . A method, comprising:
forming a crystal ingot from a crystal melt by pulling a solid crystal from the crystal melt at a pulling velocity V, wherein the crystal ingot comprises a central region and an outer radius;
while forming the crystal ingot, adjusting a ratio of the pulling velocity V to an axial temperature gradient G, wherein adjusting a ratio of the pulling velocity V to the axial temperature gradient G (ratio V/G) controls self-interstitial defects that form at the outer radius and vacancy defects that form in the central region;
determining a region of the crystal ingot that is vacancy-rich;
cutting vacancy-rich wafers from the vacancy-rich region of the crystal ingot;
evaluating the vacancy-rich wafers against a set of selection criteria; and
removing interstitials in the vacancy-rich wafers.
18 . The method of claim 17 , wherein evaluating the vacancy-rich wafers comprises analyzing an image of one or more oxidation induced stacking fault rings around edges of the vacancy-rich wafers.
19 . The method of claim 17 , wherein evaluating the vacancy-rich wafers comprises one or more of evaluating a photoluminescent wafer map, inspecting an oxidized wafer, and inspecting defects on a Secco-etched wafer.
20 . The method of claim 17 , further comprising removing oxidation induced stacking fault rings in the vacancy-rich wafers.