Zero-crossing detection circuit
A semiconductor integrated circuit device includes: a zero-crossing detection unit configured to compare a first monitoring target signal and a second monitoring target signal respectively input through diodes from a first node and a second node between which an AC signal is applied, so as to generate a comparison signal; a logic unit configured to count a period of the comparison signal and estimate a zero-cross of the AC signal using the count value, so as to generate a zero-crossing detection signal; and a monitoring unit configured to adjust the first monitoring target signal and the second monitoring target signal to be suitable for input to the zero-crossing detection unit, where a first chip, in which the monitoring unit is integrated, is cut out in a rectangular shape having a substantially equal ratio between a short side and a long side in a plan view.
1 . A semiconductor integrated circuit device comprising:
a zero-crossing detection unit configured to compare a first monitoring target signal and a second monitoring target signal respectively input through diodes from a first node and a second node between which an AC signal is applied, so as to generate a comparison signal, the comparison signal being a pulse signal with a predetermined period;
a logic unit configured to
count a pulse interval of the comparison signal to provide a count value, and estimate a zero cross of the AC signal using the count value, so as to generate a zero-crossing detection signal; and
a monitoring unit configured to adjust the first monitoring target signal and the second monitoring target signal to be suitable for input to the zero-crossing detection unit,
wherein
a first chip, in which the monitoring unit is integrated, is cut out in a rectangular shape having a substantially equal ratio between a short side and a long side in a plan view.
2 . The semiconductor integrated circuit device according to claim 1 , wherein
in the first chip, a high-withstand-voltage region having a higher withstand voltage in a substrate thickness direction than other regions is formed and, above the high-withstand-voltage region, a first pad to which the first monitoring target signal and the second monitoring target signal are input and a first feedback resistor connected to the first pad are formed.
3 . The semiconductor integrated circuit device according to claim 2 , wherein
a plurality of the high-withstand-voltage regions are formed along a first side of the first chip in a plan view of the first chip.
4 . The semiconductor integrated circuit device according to claim 3 , wherein
the plurality of the high-withstand-voltage regions are formed so as to be concentrated in a first region of the first chip in a plan view of the first chip.
5 . The semiconductor integrated circuit device according to claim 4 , wherein
in a second region of the first chip in a plan view of the first chip, a second pad for outputting a signal from the monitoring unit to the zero-crossing detection unit, a second feedback resistor connected to the second pad, a third pad connected to a ground terminal, electrostatic protection elements for protecting the second and third pads, and a fuse for adjusting a resistance value of the second feedback resistor are formed.
6 . The semiconductor integrated circuit device according to claim 5 , wherein
a plurality of second pads and a plurality of third pads are formed along a second side of the first chip orthogonal to the first side thereof in a plan view of the first chip.
7 . The semiconductor integrated circuit device according to claim 6 wherein
an inter-pad distance between the second pad and the third pad is larger than an inter-pad distance between the plurality of second pads.
8 . The semiconductor integrated circuit device according to claim 5 , wherein
in a plan view of the first chip, the second feedback resistor is formed at a position adjacent to the high-withstand-voltage region.
9 . The semiconductor integrated circuit device according to claim 5 , wherein
each of the first feedback resistor and the second feedback resistor is formed as a combination of a plurality of unit resistors.
10 . The semiconductor integrated circuit device according to claim 2 , wherein
a polysilicon resistor having a withstand voltage of 100 V or higher is used as the first feedback resistor.
11 . The semiconductor integrated circuit device according to claim 2 , wherein
the high-withstand-voltage region is a LDMOSFET region.
12 . The semiconductor integrated circuit device according to claim 11 , wherein
in the LDMOSFET region in a plan view of the first chip, a plurality of concentric ring-like drain regions and source regions are alternately formed, and the first feedback resistor is formed on a field oxide film surrounded by an innermost drain region.
13 . The semiconductor integrated circuit device according to claim 1 , wherein
a second chip, in which the zero-crossing detection unit is integrated, is cut out in a long rectangular shape in a plan view.
14 . The semiconductor integrated circuit device according to claim 13 , wherein
of a plurality of pads provided in the second chip, a plurality of pads connected to the first chip are formed to be arranged close to a first side of the second chip in a plan view of the second chip.
15 . The semiconductor integrated circuit device according to claim 13 , wherein
of a plurality of pads provided in the second chip, a plurality of pads that are not connected to the first chip are formed to be arranged close to a second side of the second chip opposite from the first side thereof in a plan view of the second chip.
16 . The semiconductor integrated circuit device according to claim 13 , wherein
the second chip has a fourth pad to which a voltage-divided signal of the first monitoring target signal is input and a fifth pad to which a voltage-divided signal of the second monitoring target signal is input, and the fourth pad and the fifth pad are provided adjacent to each other.
17 . The semiconductor integrated circuit device according to claim 16 , wherein
the second chip has a sixth pad to which a voltage-divided signal of a third monitoring target signal is input, and an inter-pad distance between the sixth pad and the fifth pad is larger than an inter-pad distance between the fourth pad and the fifth pad.
18 . The semiconductor integrated circuit device according to claim 17 , wherein
the second chip has a first output unit configured to generate a first detection result signal corresponding to the zero-crossing detection signal, a seventh pad for outputting the first detection result signal, and an eighth pad connected to a ground potential and, between the fourth pad and the seventh pad, the eighth pad is provided.
19 . The semiconductor integrated circuit device according to claim 18 , wherein
the second chip has a second output unit configured to generate a second detection result signal corresponding to the voltage-divided signal of the third monitoring target signal, a ninth pad for outputting the second detection result signal, a tenth pad connected to a power supply potential, and an eleventh pad connected to the ground potential and, between the ninth pad and the tenth pad, the eleventh pad is provided.
20 . The semiconductor integrated circuit device according to claim 18 , wherein
the zero-crossing detection unit and the first output unit are formed in a region close to the fourth to eighth pads in a plan view of the second chip.