On-chip fault detection due to malfunctions on chip pins

1 . A system-on-chip (SoC) comprising:

a first power supply pad configured to provide a first power supply to a power domain of the SoC, wherein the first power supply pad is configured to receive the first power supply from a source external to the SoC;

a first signal pad configured to receive a power ready signal from external the SoC which indicates when the first power supply to the power domain is fully powered up;

a first power detector coupled to the first power supply pad configured to provide a first power detected output, which, when asserted, indicates presence of a power supply voltage on the first power supply pad; and

a fault detection circuit coupled to the first power detector and the first signal pad and configured to generate a set of fault flags in response to monitoring a relationship between the first power detected output and a logic state of the power ready signal, wherein the fault detection circuit is configured to generate a first fault flag of the set of fault flags which indicates a fault when the first power detected output is asserted to indicate that a voltage on the first power supply pad is above a voltage supply threshold while the power ready signal is already at a logic level one, and the fault detection circuit further comprises:

a non-resettable flip flop having a data input coupled to the first signal pad, a clock input coupled to receive the first power detected output, and a data output configured to provide a stored value of the flip flop as the first fault flag of the set of fault flags, wherein the non-resettable flip flop is devoid of a reset input.

2 . The SoC of claim 1 , wherein the first power detector is configured to assert the first power detected output to a first logic state when a voltage on the first power supply pad reaches a voltage detection threshold, wherein the voltage detection threshold is less than a voltage level of the first power supply when fully powered up.

3 . The SoC of claim 2 , wherein the first power detector is configured to negate the first power detected output to a second logic state, opposite the first logic state, when the voltage on the first power supply pad is less than the voltage detection threshold to indicate absence of the power supply voltage on the first power supply pad.

4 . The SoC of claim 1 , wherein the power ready signal is a power-on-reset signal, which, when released, indicates completion of power up of the SoC during which the first power supply to the power domain has been fully powered up.

5 . The SoC of claim 4 , wherein the first power supply is a continuous power supply and the power domain is an always-on power domain which is not powered down during standby mode of the SoC.

6 . The SoC of claim 1 , wherein the external source comprises a power management circuit external to the SoC, wherein the power ready signal is a power management signal which, when asserted, indicates completion of at least a portion of a wakeup procedure from a standby mode during which the first power supply to the power domain has been fully powered up.

7 . The SoC of claim 6 , wherein the first power supply is a switchable power supply which is powered down during the standby mode of the SoC.

8 . A system-on-chip (SoC) comprising:

a first power supply pad configured to provide a first power supply to a power domain of the SoC, wherein the first power supply pad is configured to receive the first power supply from a source external to the SoC;

a first signal pad configured to receive a power ready signal from external the SoC which indicates when the first power supply to the power domain is fully powered up;

a first power detector coupled to the first power supply pad configured to provide a first power detected output, which, when asserted, indicates presence of a power supply voltage on the first power supply pad; and

a fault detection circuit coupled to the first power detector and the first signal pad and configured to generate a set of fault flags in response to monitoring a relationship between the first power detected output and a logic state of the power ready signal, wherein the fault detection circuit is configured to generate a first fault flag of the set of fault flags which indicates a fault when multiple logic state transitions of the power ready signal occur after the first power detected output is asserted to indicate the presence of the power supply voltage on the first power supply pad, wherein the fault detection circuit comprises a chain of flip flops, wherein:

a first flip flop of the chain of flip flops has a first data input coupled to receive a fixed logic value,

remaining flip flops of the chain of flip flops each have a data input coupled to a data output of a previous flip flop in the chain of flip flops,

the first power detected output is provided to an inverted reset input of each flip flop of the chain of flip flops,

the first signal pad is coupled to a clock input of each flip flop of the chain of flip flops, and

data outputs of the flip flops of the chain of flip flops are configured to provide a multi-bit value as the first fault flag of the set of fault flags.

9 . The SoC of claim 8 , wherein each flip flop of the chain of flip flops is configured to reset when the first power detected output is negated to indicate absence of the power supply voltage on the first power supply pad.

10 . The SoC of claim 8 , wherein the chain of flip flops includes N flip flops, wherein N is any integer greater than or equal to three, wherein when more than one bit of the multi-bit value provided as the first fault flag has the fixed logic value, the first fault flag indicates occurrence of a fault.

11 . The SoC of claim 8 , wherein the first power detector is configured to assert the first power detected output to a first logic state when a voltage on the first power supply pad reaches a voltage detection threshold, wherein the voltage detection threshold is less than a voltage level of the first power supply when fully powered up.

12 . The SoC of claim 11 , wherein the first power detector is configured to negate the first power detected output to a second logic state, opposite the first logic state, when the voltage on the first power supply pad is less than the voltage detection threshold to indicate absence of the power supply voltage on the first power supply pad.

13 . The SoC of claim 8 , wherein the power ready signal is a power-on-reset signal, which, when released, indicates completion of power up of the SoC during which the first power supply to the power domain has been fully powered up.

14 . The SoC of claim 13 , wherein the first power supply is a continuous power supply and the power domain is an always-on power domain which is not powered down during standby mode of the SoC.

15 . The SoC of claim 8 , wherein the external source comprises a power management circuit external to the SoC, wherein the power ready signal is a power management signal which, when asserted, indicates completion of at least a portion of a wakeup procedure from a standby mode during which the first power supply to the power domain has been fully powered up.

16 . The SoC of claim 15 , wherein the first power supply is a switchable power supply which is powered down during the standby mode of the SoC.

17 . A system-on-chip (SoC) comprising:

a first power supply pad configured to provide a first power supply to a power domain of the SoC, wherein the first power supply pad is configured to receive the first power supply from a source external to the SoC;

a first signal pad configured to receive a power ready signal from external the SoC which indicates when the first power supply to the power domain is fully powered up;

a first power detector coupled to the first power supply pad configured to provide a first power detected output, which, when asserted, indicates presence of a power supply voltage on the first power supply pad; and

a fault detection circuit coupled to the first power detector and the first signal pad and configured to generate a set of fault flags in response to monitoring a relationship between the first power detected output and a logic state of the power ready signal, wherein the fault detection circuit is configured to generate a first fault flag of the set of fault flags which indicates a fault when multiple logic state transitions of the power ready signal occur after the first power detected output is asserted to indicate the presence of the power supply voltage on the first power supply pad,

wherein the fault detection circuit comprises:

a first flip flop having a data input coupled to the first signal pad, an inverted reset input coupled to receive the first power detected output, and a clock input coupled to receive a clock signal;

a second flip flop having a data input coupled to a data output of the first flip flop, an inverted reset input coupled to receive the first power detected output, and a clock input coupled to receive a clock signal;

a third flip flop having a data output configured to provide a stored value of the flip flop as the first fault flag of the set of fault flags, and a clock input coupled to receive a clock signal; and

a logic circuit configured to:

when the data output of the third flip flop has a first logic state, provide a fixed logic value to a data input of the third flip flop, and

when the data output of the third flip flop has a second logic state, opposite the first logic state, provide a logical combination of the data outputs of the first and second flip flops to the data input of the third flip flop.

18 . The SoC of claim 17 , wherein the logical combination comprises an AND of an inverted version of the data output of the first flip flop and a data output of the second flip flop.

19 . The SoC of claim 17 , wherein the first power detector is configured to assert the first power detected output to a first logic state when a voltage on the first power supply pad reaches a voltage detection threshold, wherein the voltage detection threshold is less than a voltage level of the first power supply when fully powered up.

20 . The SoC of claim 19 , wherein the first power detector is configured to negate the first power detected output to a second logic state, opposite the first logic state, when the voltage on the first power supply pad is less than the voltage detection threshold to indicate absence of the power supply voltage on the first power supply pad.

21 . The SoC of claim 17 , wherein the power ready signal is a power-on-reset signal, which, when released, indicates completion of power up of the SoC during which the first power supply to the power domain has been fully powered up.

22 . The SoC of claim 21 , wherein the first power supply is a continuous power supply and the power domain is an always-on power domain which is not powered down during standby mode of the SoC.

23 . The SoC of claim 17 , wherein the external source comprises a power management circuit external to the SoC, wherein the power ready signal is a power management signal which, when asserted, indicates completion of at least a portion of a wakeup procedure from a standby mode during which the first power supply to the power domain has been fully powered up.

24 . The SoC of claim 23 , wherein the first power supply is a switchable power supply which is powered down during the standby mode of the SoC.