Semiconductor integrated circuit device and vehicle
A semiconductor integrated circuit device with a signal processing circuit configured to process a received signal, includes: a failure detection circuit configured to detect a failure within the semiconductor integrated circuit device; and an output terminal, wherein if the failure is not detected by the failure detection circuit, an output signal of the signal processing circuit is output externally from the output terminal, and wherein if the failure is detected by the failure detection circuit, a command notifying details of the failure is output externally from the output terminal.
1 . A semiconductor integrated circuit device, which includes a plurality of parts including a signal processing circuit configured to process a received signal, comprising:
a failure detection circuit configured to detect a failure within each of the plurality of parts; and
an output terminal,
wherein if the failure is not detected by the failure detection circuit, an output signal of the signal processing circuit is output externally from the output terminal,
wherein if the failure is detected by the failure detection circuit, a command notifying details of the failure is output externally from the output terminal, the command varying in accordance with which part among the plurality of parts the failure is detected in, and
wherein a command of a Universal Asynchronous Receiver Transmitter (UART) format is used as the command notifying the details of the failure from the output terminal.
2 . The semiconductor integrated circuit device of claim 1 , wherein if the failure is detected by the failure detection circuit, the command is periodically output externally.
3 . The semiconductor integrated circuit device of claim 1 , wherein if the failure is detected by the failure detection circuit, the output terminal is temporarily placed in a high impedance state, and then the command is output externally.
4 . The semiconductor integrated circuit device of claim 3 , wherein the high impedance state is maintained for a certain period of time.
5 . The semiconductor integrated circuit device of claim 1 , wherein the signal processing circuit includes a driver connected to the output terminal, and
wherein the driver is an open drain circuit or an open collector circuit.
6 . The semiconductor integrated circuit device of claim 5 , wherein the output terminal is configured to be externally connectable to a pull-up resistor.
7 . A vehicle comprising: a semiconductor integrated circuit device of claim 1 .
8 . A semiconductor integrated circuit device, which includes a plurality of parts including a signal processing circuit configured to process a received signal, comprising:
a failure detection circuit configured to detect a failure within each of the plurality of parts; and
an output terminal,
wherein if the failure is not detected by the failure detection circuit, an output signal of the signal processing circuit is output externally from the output terminal,
wherein if the failure is detected by the failure detection circuit, a command notifying details of the failure is output externally from the output terminal, the command varying in accordance with which part among the plurality of parts the failure is detected in, and
wherein the command notifying the details of the failure consists of a start bit that is a low level, eight data bits following the start bit, and a stop bit that is a high level following the eight data bits.
9 . The semiconductor integrated circuit device of claim 8 , wherein the command notifying the details of the failure further includes a parity bit between the eight data bits and the stop bit.
10 . The semiconductor integrated circuit device of claim 8 , wherein the failure detection circuit is configured to vary the eight data bits based on the details of the failure.
11 . The semiconductor integrated circuit device of claim 8 , wherein if the failure is detected by the failure detection circuit, the command is periodically output externally.
12 . The semiconductor integrated circuit device of claim 8 , wherein if the failure is detected by the failure detection circuit, the command notifying the details of the failure from the output terminal is output externally from the output terminal periodically with inter-byte intervals in between.
13 . The semiconductor integrated circuit device of claim 8 , wherein if the failure is detected by the failure detection circuit, the output terminal is temporarily placed in a high impedance state, and then the command is output externally.
14 . The semiconductor integrated circuit device of claim 13 , wherein the high impedance state is maintained for a certain period of time.