Integrated-circuit chip for retention cell testing
An integrated-circuit chip comprises a plurality of scan flip-flops and a retention cell. The chip is configured to have a scan-capture mode, in which the plurality of scan flip-flops and the retention cell are connected to respective functional circuitry of the integrated-circuit chip, and to have a scan-shift mode, in which the plurality of scan flip-flops and the retention cell are connected so as to form a scan chain for use during scan-chain testing of the integrated-circuit chip. The chip further comprises on-chip test circuitry arranged to generate and output a save signal, a clock signal, and a restore signal to the retention cell, for testing the retention cell during scan-chain testing of the integrated-circuit chip.
1 . An integrated-circuit chip comprising:
a plurality of scan flip-flops; and
a retention cell;
wherein the integrated-circuit chip is configured to have a scan-capture mode, in which the plurality of scan flip-flops and the retention cell are connected to respective functional circuitry of the integrated-circuit chip, and to have a scan-shift mode, in which the plurality of scan flip-flops and the retention cell are connected so as to form a scan chain for use during scan-chain testing of the integrated-circuit chip; and
wherein the integrated-circuit chip further comprises on-chip test circuitry arranged to generate and output a save signal, a clock signal, and a restore signal to the retention cell, for testing the retention cell during scan-chain testing of the integrated-circuit chip.
2 . The integrated-circuit chip of claim 1 , wherein the integrated-circuit chip is configured to receive a test data from outside the integrated-circuit chip and to load the test data to the plurality of scan flip-flops and the retention cell.
3 . The integrated-circuit chip of claim 1 , wherein the retention cell comprises a principal latch and a retention latch, wherein the principal latch and the retention latch are in different respective power domains.
4 . The integrated-circuit chip of claim 3 , wherein the principal latch is provided by a D-type flip-flop and the retention latch is a balloon latch.
5 . The integrated-circuit chip of claim 1 , wherein the retention cell comprises a save input arranged to receive the save signal from the on-chip test circuitry over a save line, and a restore input arranged to receive the restore signal from the on-chip-test circuitry over a restore line, wherein the restore input is distinct from the save input, and wherein the restore line is distinct from the save line.
6 . The integrated-circuit chip of claim 1 , further comprising a scan-enable pin for receiving a scan-enable signal from off-chip test equipment, and wherein the integrated-circuit chip is configured to switch between the scan-capture mode and the scan-shift mode at least partly in dependence on a state of the scan-enable pin.
7 . The integrated-circuit chip of claim 1 , wherein the test circuitry is configured to output the save signal, and then the clock signal, and then the restore signal, to the retention cell.
8 . The integrated-circuit chip of claim 1 , wherein the save signal is a single save pulse, the clock signal is a single clock pulse, and the restore signal is a single restore pulse.
9 . The integrated-circuit chip of claim 1 , wherein the save pulse, the clock pulse and the restore pulse are non-overlapping in time.
10 . The integrated-circuit chip of claim 1 , wherein the on-chip test circuitry is configured to output the save, clock and restore signals when the integrated-circuit chip is in the scan-capture mode and in response to the integrated-circuit chip switching from the scan-shift mode to the scan-capture mode during scan-chain testing.
11 . The integrated-circuit chip of claim 1 , configured such that the clock signal causes a principal latch of the retention cell to receive a value that is, or that depends on, a value stored in a scan flip-flop of the plurality of scan flip-flops, when the integrated-circuit chip is in the scan-capture mode.
12 . The integrated-circuit chip of claim 1 , further comprising an on-chip clock controller configured to generate a local clock signal for use by the on-chip test circuitry, and wherein the on-chip test circuitry is arranged to receive the local clock signal from the on-chip clock controller and to derive the clock signal for output to the retention cell from the received local clock signal.
13 . The integrated-circuit chip of claim 12 , wherein the on-chip test circuitry is further configured to use the local clock signal to synchronize the save signal, clock signal and restore signal output by the on-chip test circuitry to the retention cell.
14 . The integrated-circuit chip of claim 1 , further comprising test-enable circuitry configured to generate a test-enable signal for indicating that retention testing is to be performed during the scan-chain testing, and wherein the test-enable circuitry is configured to output the test-enable signal at least partly in response to a signal received from outside the chip.
15 . The integrated-circuit chip of claim 14 , wherein the test-enable circuitry is configured to be responsive to a signal received over a test access port of the integrated-circuit chip and/or received as a control bit within test data received at a scan-input pin of the integrated-circuit chip.
16 . The integrated-circuit chip of claim 14 , wherein the test-enable circuitry comprises a control-bit scan flip-flop arranged to be part of the scan chain and to output data values to the plurality of scan flip-flops and the retention cell in the scan-shift mode, and wherein the integrated-circuit chip is configured to determine whether to issue the save and restore signals to the retention cell at least partly in dependence on a value stored in the control-bit scan flip-flop.
17 . The integrated-circuit chip of claim 1 , comprising a plurality of retention cells, each arranged to receive the save, clock and restore signals from the on-chip test circuitry.
18 . The integrated-circuit chip of claim 1 , wherein the retention cell is at an end of the scan chain when in the scan-shift mode, optionally in a sequence with one or more further retention cells.
19 . A method of operating an integrated-circuit chip, wherein the integrated-circuit chip comprises:
a plurality of scan flip-flops;
a retention cell; and
on-chip test circuitry configured to generate and output save, clock and restore signals to the retention cell,
the method comprising, during a scan-chain testing of the integrated-circuit chip:
operating the integrated-circuit chip in a scan-shift mode, in which the plurality of scan flip-flops and the retention cell are connected so as to form a scan chain;
operating the integrated-circuit chip in a scan-capture mode, in which the plurality of scan flip-flops and the retention cell are connected to respective functional circuitry of the integrated-circuit chip; and
using the on-chip test circuitry to generate and output a save signal, a clock signal and a restore signal to the retention cell.
20 . The method of claim 19 , wherein the scan-chain testing comprises automatic test pattern generation (ATPG)-based testing.