Array substrate and total reflection liquid crystal display panel

1 . An array substrate, comprising:

a substrate;

a driving circuit layer disposed on the substrate;

a planarization layer disposed on a side of the driving circuit layer away from the substrate, wherein a side of the planarization layer away from the substrate has an uneven surface which is at least partially uneven; and

a reflection electrode layer disposed on the side of the planarization layer away from the substrate and disposed along the uneven surface of the planarization layer in an uneven shape,

wherein the uneven surface is configured to reflect light from the reflection electrode layer,

wherein the planarization layer has a plurality of convex structures or concave structures, a minimum distance between adjacent concave structures or between adjacent convex structures is greater than 0 and less than or equal to 30 μm, the driving circuit layer includes a first metal layer, a gate insulation layer, a semiconductor layer, an ohmic contact layer, and a second metal layer sequentially stacked on the substrate, the first metal layer includes a scanning line-related pattern, and the second metal layer includes a data line-related pattern,

wherein the first metal layer includes a plurality of patterned gate electrodes, the semiconductor layer includes a plurality of semiconductor patterns disposed opposite to the gate electrodes,

wherein distances between adjacent convex structures or between adjacent concave structures comprise a plurality of values that are different from one another,

wherein the reflection electrode layer comprises a first electrode layer, a second electrode layer and a third electrode layer, the first electrode layer is disposed between the second electrode layer and the third electrode layer, a material of the first electrode layer comprises an alloy of any one or more selected from gold, silver, copper, and aluminum, and materials of the second electrode layer and the third electrode layer are transparent conductive metal oxides,

wherein first portions of the first electrode layer, the second electrode layer and the third electrode layer cover a surface of the planarization layer away from the substrate, second portions of the first electrode layer, the second electrode layer and the third electrode layer cover a surface of the first metal layer away from the substrate, and third portions of the first electrode layer, the second electrode layer and the third electrode layer cover a surface of the gate insulation layer away from the substrate, and

wherein the first portion of the second electrode layer is in contact with the surface of the planarization layer away from the substrate, the second portion of the second electrode layer is in contact with the surface of the first metal layer away from the substrate, and the third portion of the second electrode layer is in contact with the surface of the gate insulation layer away from the substrate.

2 . The array substrate as claimed in claim 1 , wherein the plurality of convex structures or the plurality of concave structures are distributed in an array manner on the side of the planarization layer away from the substrate.

3 . The array substrate as claimed in claim 2 , wherein under a condition that the planarization layer has a plurality of convex structures, the plurality of convex structures have a curved surface that is convex, and an included angle between a tangent of any point on the curved surface and a flat surface of the planarization layer is less than or equal to 10°.

4 . The array substrate as claimed in claim 2 , wherein under a condition that the planarization layer has a plurality of concave structures, the plurality of concave structures have a curved surface that is concave, and an included angle between a tangent of any point on the curved surface and a flat surface of the planarization layer is less than or equal to 10°.

5 . The array substrate as claimed in claim 2 , wherein the plurality of convex structures or the plurality of concave structures are distributed continuously or spaced apart on the surface of the planarization layer away from the substrate.

6 . The array substrate as claimed in claim 5 , wherein under a condition that the planarization layer has a plurality of convex structures, the plurality of convex structures are spaced apart and arranged in rows along a first direction, the plurality of convex structures are spaced apart and arranged in columns along a second direction, and the first direction is different from the second direction; and

wherein any two adjacent rows or any two adjacent columns of the plurality of convex structures are disposed side by side, or any two adjacent rows or any two adjacent columns of the plurality of convex structures are disposed in a stagger manner.

7 . The array substrate as claimed in claim 5 , wherein under a condition that the planarization layer has a plurality of concave structures, the plurality of concave structures are spaced apart and arranged in rows along a first direction, the plurality of concave structures are spaced apart and arranged in columns along a second direction, and the first direction is different from the second direction; and

wherein any two adjacent rows or any two adjacent columns of the plurality of concave structures are disposed side by side, or any two adjacent rows or any two adjacent columns of the plurality of concave structures are disposed in a stagger manner.

8 . The array substrate as claimed in claim 2 , wherein a shape of the plurality of convex structures or the plurality of concave structures is any one of a triangle, a quadrilateral, a pentagon, a hexagon, a circle, or an ellipse.

9 . A total reflection liquid crystal display panel, comprising an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate, wherein the color filter substrate includes an opposite substrate, and includes a color filter layer, a protective layer, a common electrode, and spacers disposed on a side of the opposite substrate near the array substrate, and wherein the array substrate comprises:

a substrate;

a driving circuit layer disposed on the substrate;

a planarization layer disposed on a side of the driving circuit layer away from the substrate, wherein a side of the planarization layer away from the substrate has an uneven surface which is at least partially uneven; and

a reflection electrode layer disposed on the side of the planarization layer away from the substrate and disposed along the uneven surface of the planarization layer in an uneven shape,

wherein the uneven surface is configured to reflect light out of the total reflection liquid crystal display panel,

wherein the planarization layer has a plurality of convex structures or concave structures, a minimum distance between adjacent concave structures or between adjacent convex structures is greater than 0 and less than or equal to 30 μm, the driving circuit layer includes a first metal layer, a gate insulation layer, a semiconductor layer, an ohmic contact layer, and a second metal layer sequentially stacked on the substrate, the first metal layer includes a scanning line-related pattern, and the second metal layer includes a data line-related pattern,

wherein the first metal layer includes a plurality of patterned gate electrodes, the semiconductor layer includes a plurality of semiconductor patterns disposed opposite to the gate electrodes,

wherein distances between adjacent convex structures or between adjacent concave structures comprise a plurality of values that are different from one another,

wherein the reflection electrode layer comprises a first electrode layer, a second electrode layer and a third electrode layer, the first electrode layer is disposed between the second electrode layer and the third electrode layer, a material of the first electrode layer comprises an alloy of any one or more selected from gold, silver, copper, and aluminum, and materials of the second electrode layer and the third electrode layer are transparent conductive metal oxides,

wherein first portions of the first electrode layer, the second electrode layer and the third electrode layer cover a surface of the planarization layer away from the substrate, second portions of the first electrode layer, the second electrode layer and the third electrode layer cover a surface of the first metal layer away from the substrate, and third portions of the first electrode layer, the second electrode layer and the third electrode layer cover a surface of the gate insulation layer away from the substrate, and

wherein the first portion of the second electrode layer is in contact with the surface of the planarization layer away from the substrate, the second portion of the second electrode layer is in contact with the surface of the first metal layer away from the substrate, and the third portion of the second electrode layer is in contact with the surface of the gate insulation layer away from the substrate.

10 . The total reflection liquid crystal display panel as claimed in claim 9 , wherein the plurality of convex structures or the plurality of concave structures are distributed in an array manner on the side of the planarization layer away from the substrate.

11 . The total reflection liquid crystal display panel as claimed in claim 10 , wherein under a condition that the planarization layer has a plurality of convex structures, the plurality of convex structures have a curved surface that is convex, and an included angle between a tangent of any point on the curved surface and a flat surface of the planarization layer is less than or equal to 10°.

12 . The total reflection liquid crystal display panel as claimed in claim 10 , wherein under a condition that the planarization layer has a plurality of concave structures, the plurality of concave structures have a curved surface that is concave, and an included angle between a tangent of any point on the curved surface and a flat surface of the planarization layer is less than or equal to 10°.

13 . The total reflection liquid crystal display panel as claimed in claim 10 , wherein the plurality of convex structures or the plurality of concave structures are distributed continuously or spaced apart on the surface of the planarization layer away from the substrate.

14 . The total reflection liquid crystal display panel as claimed in claim 13 , wherein under a condition that the planarization layer has a plurality of convex structures, the plurality of convex structures are spaced apart and arranged in rows along a first direction, the plurality of convex structures are spaced apart and arranged in columns along a second direction, and the first direction is different from the second direction; and

wherein any two adjacent rows or any two adjacent columns of the plurality of convex structures are disposed side by side, or any two adjacent rows or any two adjacent columns of the plurality of convex structures are disposed in a stagger manner.

15 . A total reflection liquid crystal display panel, comprising an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate, wherein the color filter substrate includes an opposite substrate, and includes a color filter layer, a protective layer, a common electrode, and spacers disposed on a side of the opposite substrate near the array substrate, and wherein the array substrate comprises:

a substrate;

a driving circuit layer disposed on the substrate;

a planarization layer disposed on a side of the driving circuit layer away from the substrate, wherein a side of the planarization layer away from the substrate has an uneven surface which is at least partially uneven; and

a reflection electrode layer disposed on the side of the planarization layer away from the substrate and disposed along the uneven surface of the planarization layer in an uneven shape,

wherein the uneven surface is configured to reflect light from the reflection electrode layer,

wherein the planarization layer has a plurality of convex structures or concave structures, a minimum distance between adjacent concave structures or between adjacent convex structures is greater than 0 and less than or equal to 30 μm, the driving circuit layer includes a first metal layer, a gate insulation layer, a semiconductor layer, an ohmic contact layer, and a second metal layer sequentially stacked on the substrate, the first metal layer includes a scanning line-related pattern, and the second metal layer includes a data line-related pattern,

wherein the first metal layer includes a plurality of patterned gate electrodes, the semiconductor layer includes a plurality of semiconductor patterns disposed opposite to the gate electrodes,

wherein distances between adjacent convex structures or between adjacent concave structures comprise a plurality of values that are different from one another,

wherein the reflection electrode layer comprises a first electrode layer, a second electrode layer and a third electrode layer, the first electrode layer is disposed between the second electrode layer and the third electrode layer, a material of the first electrode layer comprises an alloy of any one or more selected from gold, silver, copper, and aluminum, and materials of the second electrode layer and the third electrode layer are transparent conductive metal oxides,

wherein first portions of the first electrode layer, the second electrode layer and the third electrode layer cover a surface of the planarization layer away from the substrate, second portions of the first electrode layer, the second electrode layer and the third electrode layer cover a surface of the first metal layer away from the substrate, and third portions of the first electrode layer, the second electrode layer and the third electrode layer cover a surface of the gate insulation layer away from the substrate,

wherein the first portion of the second electrode layer is in contact with the surface of the planarization layer away from the substrate, the second portion of the second electrode layer is in contact with the surface of the first metal layer away from the substrate, and the third portion of the second electrode layer is in contact with the surface of the gate insulation layer away from the substrate,

wherein a shape of the plurality of convex structures or the plurality of concave structures is a hexagon,

wherein under a condition that the planarization layer has the plurality of concave structures, the plurality of concave structures are spaced apart and arranged in rows along a first direction, the plurality of concave structures are spaced apart and arranged in columns along a second direction, and the first direction is different from the second direction, and

wherein any two adjacent rows or any two adjacent columns of the plurality of concave structures are disposed in a stagger manner.