Overshoot-free fast start-up bandgap reference circuit, chip, and electronic device
An overshoot-free fast start-up bandgap reference circuit ( 100 ), a chip, and an electronic device. The bandgap reference circuit ( 100 ) comprises a bias current generating unit ( 101 ) and a reference core unit ( 102 ), wherein an output end of the bias current generating unit ( 101 ) is connected to an input end of the reference core unit ( 102 ), the bias current generating unit ( 101 ) generates a bias current (I BIAS ) unrelated to the voltage of a power supply and having a zero temperature coefficient, the bias current (I BIAS ) is an input signal of the reference core unit ( 102 ), and the reference core unit ( 102 ) generates a pre-charging current on the basis of the input bias current (I BIAS ) and implements overshoot-free fast start-up by means of employing pre-charging.
1 . An overshoot-free fast start-up bandgap reference circuit, comprising a bias current generation unit ( 101 ) and a reference core unit ( 102 ), wherein an output end of the bias current generation unit ( 101 ) is connected to an input end of the reference core unit ( 102 );
the bias current generation unit ( 101 ) generates a bias current that is not related to a power supply voltage and has a zero-temperature coefficient, used as an input signal of the reference core unit ( 102 );
the reference core unit ( 102 ) comprises a second starting circuit ( 401 ) and a reference core circuit ( 402 ); and an output end of the second starting circuit ( 401 ) is connected to an input end of the reference core circuit ( 402 ); the second starting circuit ( 401 ) comprises a bias current injection branch ( 501 ), a proportional mirror and injection branch ( 502 ), and a feedback current cut-off control branch ( 503 ); the bias current injection branch ( 501 ) receives the bias current output by the bias current generation unit ( 101 ); the proportional mirror and injection branch ( 502 ) proportionally mirrors the bias current to form a pre-charge current and injects the pre-charge current into the reference core circuit ( 402 ); and the feedback current cut-off control branch ( 503 ) reduces the pre-charge current to zero after the reference core circuit ( 402 ) is started.
2 . The overshoot-free fast start-up bandgap reference circuit according to claim 1 , wherein
the bias current generation unit ( 101 ) comprises a first starting circuit ( 201 ) and a bias current generation circuit ( 202 ); and an output end of the first starting circuit ( 201 ) is connected to an input end of the bias current generation circuit ( 202 ).
3 . The overshoot-free fast start-up bandgap reference circuit according to claim 2 , wherein
the first starting circuit ( 201 ) comprises a starting current generation branch ( 301 ), a proportional mirror and injection branch ( 302 ), and a feedback current cut-off control branch ( 303 ); the starting current generation branch ( 301 ) generates a starting current, and the proportional mirror and injection branch ( 302 ) proportionally mirrors the starting current and injects the starting current into the bias current generation circuit ( 202 ); and after the bias current generation circuit ( 202 ) is started, the feedback current cut-off control branch ( 303 ) reduces the proportionally mirrored and injected current to zero by using feedback current cut-off control.
4 . The overshoot-free fast start-up bandgap reference circuit according to claim 2 , wherein
the bias current generation circuit ( 202 ) comprises a third NMOS transistor (MN3), a fourth NMOS transistor (MN4), a fifth NMOS transistor (MN5), a sixth NMOS transistor (MN6), a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third PMOS transistor (MP3), a fourth PMOS transistor (MP4), a fifth PMOS transistor (MP5), a sixth PMOS transistor (MP6), and a thirteenth PMOS transistor (MP13);
the third NMOS transistor (MN3), the fourth NMOS transistor (MN4), the fifth NMOS transistor (MN5), and the sixth NMOS transistor (MN6) form NMOS current proportional mirror pair transistors in a cascode structure;
the third PMOS transistor (MP3), the fourth PMOS transistor (MP4), the fifth PMOS transistor (MP5), and the sixth PMOS transistor (MP6) form a first set of PMOS current proportional mirror pair transistors in a cascode structure; and
the first PMOS transistor (MP1), the second PMOS transistor (MP2), the third PMOS transistor (MP3), and the fourth PMOS transistor (MP4) form a second set of PMOS current proportional mirror pair transistors in a cascode structure.
5 . The overshoot-free fast start-up bandgap reference circuit according to claim 4 , wherein the bias current generation circuit ( 202 ) further comprises a first resistor (R1), a second resistor (R2), and a third resistor (R3); an end of the first resistor (R1) is connected to a source of the third PMOS transistor (MP3), and the other end of the first resistor (R1) is connected to a power supply end; an end of the second resistor (R2) is connected to a drain of the fifth NMOS transistor (MN5), and the other end of the second resistor (R2) is separately connected to a drain of the sixth PMOS transistor (MP6) and a gate of the fifth PMOS transistor (MP5); and an end of the third resistor (R3) is separately connected to a drain of the sixth NMOS transistor (MN6) and a gate of the fourth NMOS transistor (MN4), and the other end of the third resistor (R3) is separately connected to a gate of the sixth NMOS transistor (MN6) and a drain of the fourth PMOS transistor (MP4).
6 . The overshoot-free fast start-up bandgap reference circuit according to claim 5 , wherein
the first resistor (R1), the second resistor (R2), and the third resistor (R3) each have different temperature coefficients.
7 . The overshoot-free fast start-up bandgap reference circuit according to claim 1 , wherein
the pre-charge current is divided into three currents; a first pre-charge current is a drain output current of a thirty-third PMOS transistor (MP13), and is injected into an output end of the reference core circuit ( 402 ); a second pre-charge current is a drain output current of a thirty-fourth PMOS transistor (MP14), and is injected into a non-inverting input end of a first operational amplifier in the reference core circuit ( 402 ); and a third pre-charge current is a drain output current of a thirty-fifth PMOS transistor (MP15), and is injected into an inverting input end of the first operational amplifier in the reference core circuit ( 402 ).
8 . The overshoot-free fast start-up bandgap reference circuit according to claim 1 , wherein
the feedback current cut-off control branch ( 503 ) comprises a twenty-second NMOS transistor (MN2), a thirty-first PMOS transistor (MP11), and a thirty-second PMOS transistor (MP12); a drain of the twenty-second NMOS transistor (MN2) is connected to a drain of the thirty-first PMOS transistor (MP11) as well as a gate and a drain of the thirty-second PMOS transistor (MP12); a source of the thirty-first PMOS transistor (MP11) is connected to a power supply end; a gate of the thirty-first PMOS transistor (MP11) is connected to an output end of a first operational amplifier in the reference core circuit ( 402 ); and
when the reference core circuit ( 402 ) is started, a current on the thirty-first PMOS transistor (MP11) is greater than a current on the twenty-second NMOS transistor (MN2), a gate voltage of the thirty-second PMOS transistor (MP12) is increased to VDD, and the pre-charge current is reduced to zero.
9 . An integrated circuit chip, comprising the overshoot-free fast start-up bandgap reference circuit according to claim 1 .
10 . An electronic device, comprising the overshoot-free fast start-up bandgap reference circuit according to claim 1 .