IP Library › Granted Patent US 12663826
Granted Patent B2
US 12663826 · App. 18/672,398 · Granted Jun 23, 2026

Voltage reference circuit

Inventors: Bei-Shing Lien (Taipei City, TW); Szu-Lin Liu (Hsinchu City, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
G05F3/262G05F1/468G05F1/567
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Quick Facts
Patent No.
US 12663826
App. No.
18/672,398
Granted
Jun 23, 2026
Kind
B2
Abstract

A bandgap voltage reference circuit is provided. In one example, a cell includes a first device including a first plurality of MOSFETs connected in series The cell further includes a second device including a second plurality of MOSFETs connected in series. The second device connects in series with the first device. The second plurality of MOSFETs has a second Vt that is higher than the first Vt. The cell further includes a reference node connected between the first stack gate device and the second stack gate device.

Claims (37)

1 . A cell, comprising:

a first plurality of MOSFETs connected in series with each gate of the first plurality of MOSFETs connected to a first node, wherein a source/drain terminal of one of the first plurality of MOSFETs is connected to the first node, each of the MOSFETs of the first plurality of MOSFETs having a first threshold voltage (Vt);

a second plurality of MOSFETs connected in series, the second plurality of MOSFETs connected in series with the first plurality of MOSFETs, each of the MOSFETs of the second plurality of MOSFETs having a second Vt that is higher than the first Vt;

a reference node connected at a junction of the first plurality of MOSFETs and the second plurality of MOSFETs, the reference node being separate from the first node; and

a trimming circuit configured to adjust a temperature coefficient of a reference voltage at the reference node, the trimming circuit including two or more inverters, the two or more inverters including a source/drain terminal connected to the first node, and at least one of the inverters connected to the gates of the second plurality of MOSFETs.

2 . The cell of claim 1 , wherein the second plurality of MOSFETS are standard threshold voltage transistors (SVT) and the first plurality of MOSFETs are one of low threshold voltage transistors (LVT), ultra-low threshold voltage transistors (ULVT), or extremely low threshold voltage transistors (ELVT).

3 . The cell of claim 1 , wherein the second plurality of MOSFETs are LVT transistors and the first plurality of MOSFETs are ULVT transistors or ELVT transistors.

4 . The cell of claim 1 , wherein the second plurality of MOSFETs are ULVT transistors and the first plurality of MOSFETs are ELVT transistors.

5 . The cell of claim 1 , wherein the trimming circuit further includes a MOSFET connected in parallel with the second plurality of MOSFETs, and wherein the two or more inverters connect to a gate of the MOSFET, and wherein the two or more inverters connect to the first node.

6 . The cell of claim 1 , wherein the second plurality of MOSFETs includes more MOSFETs than the first plurality of MOSFETs.

7 . The cell of claim 1 , further comprising:

an additional two or more inverters connected to the gates of one or more MOSFETS connected in parallel with the second plurality of MOSFETS.

8 . The cell of claim 7 , wherein the one or more MOSFETS vary the temperature coefficient of the cell.

9 . A circuit, comprising:

a voltage terminal;

a first current mirror including three MOSFETs;

a second current mirror connected to a first MOSFET and a second MOSFET of the first current mirror;

a cell including:

a first plurality of MOSFETs connected in series with each gate of the first plurality of MOSFETs connected to a third transistor of the first current mirror forming a first node, wherein a source/drain terminal of one of the first plurality of MOSFETs is connected to the third MOSFET of the first current mirror, each of the MOSFETs of the first plurality of MOSFETs having a first threshold voltage (Vt);

a second plurality of MOSFETs connected in series, the second plurality of MOSFETs connected in series with the first plurality of MOSFETs, each of the MOSFETs of the second plurality of MOSFETs having a second Vt that is higher than the first Vt; and

a reference node connected at a junction of the first plurality of MOSFETs and the second plurality of MOSFETs, the reference node being separate from the first node; and

a trimming circuit configured to adjust a temperature coefficient of a reference voltage at the reference node, the trimming circuit including two or more inverters, the two or more inverters including a source/drain terminal connected to the first node, and at least one of the inverters connected to the gates of the second plurality of MOSFETs.

10 . The circuit of claim 9 , wherein the first plurality of MOSFETs and the second plurality of MOSFETS include ten or more MOSFETs.

11 . The circuit of claim 10 , wherein the second plurality of MOSFETS are standard threshold voltage transistors (SVT) and the first plurality of MOSFETs are one of low threshold voltage transistors (LVT), ultra-low threshold voltage transistors (ULVT), or extremely low threshold voltage transistors (ELVT).

12 . The circuit of claim 10 , wherein the second plurality of MOSFETs are LVT transistors and the first plurality of MOSFETs are ULVT transistors or ELVT transistors.

13 . The circuit of claim 10 , wherein the second plurality of MOSFETs are ULVT transistors and the first plurality of MOSFETs are ELVT transistors.

14 . The circuit of claim 10 , wherein the first current mirror and second current mirror form a proportional to absolute temperature (PTAT) cell.

15 . The circuit of claim 9 , wherein the trimming circuit further includes a MOSFET connected in parallel with the second plurality of MOSFETs, and wherein the two or more inverters connect to a gate of the MOSFET, and wherein the two or more inverters connect to the first node.

16 . The circuit of claim 9 , wherein the second plurality of MOSFETs includes more MOSFETs than the first plurality of MOSFETs.

17 . The circuit of claim 9 , wherein the cell further comprises:

an additional two or more inverters connected to the gates of one or more MOSFETS connected in parallel with the second plurality of MOSFETS.

18 . The circuit of claim 17 , wherein the one or more MOSFETS vary the temperature coefficient of the cell.

19 . A method, comprising:

receiving an input voltage by a first plurality of MOSFETs with a common gate forming a first node, the first plurality of MOSFETs connected in series with a second plurality of MOSFETs, each of the MOSFETs of the first plurality of MOSFETs having a first threshold voltage (Vt);

outputting a reference voltage at a junction between the first plurality of MOSFETs and the second plurality of MOSFETs, each of the MOSFETs of the second plurality of MOSFETs having a second Vt that is higher than the first Vt, wherein the junction forms a reference node that is separate from the first node; and

adjusting a temperature coefficient of the reference voltage by connecting one or more MOSFETs in parallel with the second plurality of MOSFETs, wherein adjusting the temperature coefficient includes providing an on signal to at least one of two or more inverters including a source/drain terminal connected to the first node, and wherein at least one of the inverters is connected to the gates of the second plurality of MOSFETs.

20 . The method of claim 19 , wherein providing the on signal trims the temperature coefficient based on a number of trimming bits.