Automatic on-die frequency tuning using tunable replica circuits
Embodiments herein relate to optimizing the operation of multiple integrated circuits (ICs) operating in parallel. In one aspect, the ICs are arranged in a voltage-stacked configuration, and an operating frequency of each IC is controlled using a tunable replica circuit to stabilize its voltage drop. The tunable replica circuit mimics a critical path on the IC. In another aspect, an IC is divided into top and bottom portions which are in respective voltage domains on a substrate. The substrate include a deep n-well region for the higher voltage domain. In another aspect, a physically unclonable function (PUF) is used to generate identifiers for each IC among a multiple ICs on a board. Entropy sources of the PUF generate bits of the identifiers. Unstable entropy sources are identified and their bits are masked out.
1 . An apparatus, comprising:
a plurality of die in a voltage-stacked configuration; and
on each die, a tunable replica circuit comprising a tunable delay circuit, the tunable replica circuit is to determine a delay of the tunable delay circuit and to provide a first control signal based on the delay, and a phase-locked loop (PLL) to output a clock signal with a target frequency to a plurality of processing engines on the die, wherein when the first control signal is provided to the PLL, the PLL is responsive to the first control signal to adjust the target frequency of the clock signal to regulate a voltage drop of the die.
2 . The apparatus of claim 1 , wherein:
for one or more of the die, the delay of the tunable delay is set as a product of a predetermined multiplier and a critical path of a plurality of integrated circuits on the die.
3 . The apparatus of claim 1 , wherein:
for one or more of the die, the tunable delay circuit comprises a chain of tunable inverters.
4 . The apparatus of claim 1 , wherein:
for one or more of the die, the tunable delay circuit comprises a digitally programmable delay generator.
5 . The apparatus of claim 1 , wherein:
for one or more of the die, the tunable delay circuit comprises a tunable data path mimicking a critical path of a plurality of integrated circuits on the die, and the tunable data path comprise a plurality of carry-save adders.
6 . The apparatus of claim 1 , wherein:
for one or more of the die, the tunable delay circuit comprises a data path mimicking a critical path of a plurality of integrated circuits on the die with a tunable launch/capture clock.
7 . The apparatus of claim 1 , wherein:
the first control signal is to instruct the PLL to increase the target frequency of the clock signal if the delay exceeds an upper threshold.
8 . The apparatus of claim 1 , wherein:
the first control signal is to instruct the PLL to decrease the target frequency of the clock signal if the delay falls below a lower threshold.
9 . The apparatus of claim 1 , wherein:
for each die, the plurality of processing engines are to work in parallel on computations of a cryptographic hashing algorithm.
10 . The apparatus of claim 1 , wherein:
the plurality of die are arranged in rows, each row comprising multiple die;
the rows are in a voltage-stacked configuration; and
the PLL is responsive to the first control signal to adjust the target frequency of the clock signal to regulate a voltage drop of each row.
11 . The apparatus of claim 1 , further comprising:
for one or more of the die, a sense circuit to monitor a voltage drop of the die, wherein a controller is to query the sense circuits of the one or more of the die to obtain the voltage drop and to provide a second control signal based on the voltage drop, wherein when the second control signal is provided to the PLL, and the PLL is responsive to the second control signal in place of the first control signal to adjust the target frequency of the clock signal to regulate the voltage drop of the die.
12 . The apparatus of claim 11 , wherein:
for the one or more of the die, the second control signal is to replace the first control signal when the voltage drop of the one or more of the die is beyond at least one of a lower threshold or an upper threshold.
13 . The apparatus of claim 1 , wherein:
the PLLs of the plurality of die are to adjust the frequencies of the clock signals to equalize a voltage drop of each die.