Input/output capacitance reduction with negative impedance
Data transfer rates input to and output from electronic devices are a function of I/O pad circuit structure. The load capacitance of an I/O pad may reduce the bandwidth of an I/O circuit. A reduced pad capacitance circuit may be used to reduce or eliminate the positive and physical pad capacitance associated with a capacitive pad. This negative capacitance reduces or minimizes poor signal quality arising from large pad capacitance. This improved signal may be fed into a comparator, where the signal may be improved further using an equalizer. The use of negative capacitance circuit will increase the transmit and receive signaling quality of I/O interfaces.
1 . A circuit comprising:
a signal conductor pad to receive an input signal;
a pad capacitor conductively coupled to the signal conductor pad; and
a negative impedance circuit including:
an operational amplifier with a non-inverting opamp input conductively coupled to receive the input signal from the pad capacitor;
a direct current blocking capacitor conductively coupled between the non-inverting opamp input and an opamp output;
a first resistor conductively coupled between an inverting opamp input and a ground; and
a second resistor conductively coupled between the inverting opamp input and the opamp output.
2 . The circuit of claim 1 , wherein:
the pad capacitor is associated with a pad capacitance; and
the negative impedance circuit is configured to negate the pad capacitance.
3 . The circuit of claim 1 , further including a comparator circuit, the comparator circuit including:
a first comparator terminal coupled to the negative impedance circuit and the signal conductor pad;
a second comparator terminal coupled to a reference input; and
an equalizer to generate an equalized output signal based on the input signal.
4 . The circuit of claim 3 , wherein the equalizer includes at least one of a continuous time linear equalizer and a decision feedback equalizer.
5 . The circuit of claim 4 , wherein:
the direct current blocking capacitor is associated with a blocking capacitance; and
the blocking capacitance is selected to provide an improvement in performance of the equalized output signal.
6 . The circuit of claim 5 , wherein:
the first resistor is associated with a first resistance;
the second resistor is associated with a second resistance; and
the first resistance is selected to be substantially double the second resistance.
7 . The circuit of claim 1 , further including an amplitude sensor circuit coupled between the negative impedance circuit and the pad capacitor, the amplitude sensor circuit to:
determine that the input signal transgresses an amplitude threshold; and
decouple the negative impedance circuit and the pad capacitor in response to the determination that the input signal transgresses the amplitude threshold.
8 . The circuit of claim 1 , further including a saturation sensor circuit coupled between the negative impedance circuit and the pad capacitor and coupled to the opamp output of the negative impedance circuit, the saturation sensor circuit to:
determine that the opamp output transgresses a saturation threshold; and
decouple the negative impedance circuit and the pad capacitor in response to the determination that the opamp output transgresses the saturation threshold.
9 . A method comprising:
receiving an input signal from a signal conductor pad; and
generating a capacitance-cancelled signal at a capacitance cancelling circuit based on the input signal, the capacitance cancelling circuit including:
a pad capacitor conductively coupled to the signal conductor pad; and
a negative impedance circuit including:
an operational amplifier with a non-inverting opamp input conductively coupled to receive the input signal from the pad capacitor;
a direct current blocking capacitor conductively coupled between the non-inverting opamp input and an opamp output;
a first resistor conductively coupled between an inverting opamp input and a ground; and
a second resistor conductively coupled between the inverting opamp input and the opamp output.
10 . The method of claim 9 , wherein:
the pad capacitor is associated with a pad capacitance; and
the negative impedance circuit is configured to negate the pad capacitance.
11 . The method of claim 9 , further including generate an equalized output signal at a comparator circuit, the comparator circuit including:
a first comparator terminal coupled to the negative impedance circuit and the signal conductor pad;
a second comparator terminal coupled to a reference input; and
an equalizer to generate an equalized output signal based on the capacitance-cancelled signal.
12 . The method of claim 11 , wherein the equalizer includes at least one of a continuous time linear equalizer and a decision feedback equalizer.
13 . The method of claim 12 , wherein:
the direct current blocking capacitor is associated with a blocking capacitance; and
the blocking capacitance is selected to provide an improvement in performance of the equalized output signal.
14 . The method of claim 13 , wherein:
the first resistor is associated with a first resistance;
the second resistor is associated with a second resistance; and
the first resistance is selected to be substantially double the second resistance.
15 . The method of claim 9 , further including:
determining that the input signal transgresses an amplitude threshold at an amplitude sensor circuit coupled between the negative impedance circuit and the pad capacitor; and
decoupling the negative impedance circuit and the pad capacitor in response to determining that the input signal transgresses the amplitude threshold.
16 . The method of claim 9 , further including determining that the opamp output transgresses a saturation threshold at a saturation sensor circuit, the saturation sensor circuit coupled between the negative impedance circuit and the pad capacitor and coupled to the opamp output of the negative impedance circuit; and
decoupling the negative impedance circuit and the pad capacitor in response to determining that the opamp output transgresses the saturation threshold.
17 . A circuit comprising:
a signal conductor pad to receive an input signal;
a capacitance cancelling circuit to generate a capacitance-cancelled signal based on an input signal received from the signal conductor pad, wherein the capacitance cancelling circuit includes:
a pad capacitor conductively coupled to the signal conductor pad to receive the input signal; and
a negative impedance circuit including:
an operational amplifier including a non-inverting opamp input conductively coupled to receive the input signal from the pad capacitor, an inverting opamp input, and an opamp output;
a direct current blocking capacitor conductively coupled between the non-inverting opamp input and the opamp output;
an impedance-setting network conductively coupled to the inverting opamp input to define a negative impedance characteristic of the negative impedance circuit; and
a comparator circuit to generate an equalized output based on the capacitance-cancelled signal.
18 . The circuit of claim 17 , the comparator circuit including:
a first comparator terminal coupled to the negative impedance circuit and the signal conductor pad;
a second comparator terminal coupled to a reference input; and
an equalizer to generate an equalized output signal based on the input signal.
19 . The circuit of claim 18 , wherein the equalizer includes at least one of a continuous time linear equalizer and a decision feedback equalizer.
20 . The circuit of claim 19 , wherein:
the direct current blocking capacitor is associated with a blocking capacitance; and
the blocking capacitance is selected to provide an improvement in performance of the equalized output signal.
21 . The circuit of claim 20 , further including:
a first resistor conductively coupled between an inverting opamp input and a ground, the first resistor is associated with a first resistance;
a second resistor conductively coupled between the inverting opamp input and the opamp output, the second resistor is associated with a second resistance; and
the first resistance is selected to be substantially double the second resistance.
22 . The circuit of claim 17 , wherein the capacitance cancelling circuit further includes an amplitude sensor circuit coupled between the negative impedance circuit and the pad capacitor, the amplitude sensor circuit to:
determine that the input signal transgresses an amplitude threshold; and
decouple the negative impedance circuit and the pad capacitor in response to the determination that the input signal transgresses the amplitude threshold.
23 . The circuit of claim 17 , wherein the capacitance cancelling circuit further includes a saturation sensor circuit coupled between the negative impedance circuit and the pad capacitor and coupled to the opamp output of the negative impedance circuit, the saturation sensor circuit to:
determine that the opamp output transgresses a saturation threshold; and
decouple the negative impedance circuit and the pad capacitor in response to the determination that the opamp output transgresses the saturation threshold.