IP Library › Granted Patent US 12663892
Granted Patent B1
US 12663892 · App. 19/232,876 · Granted Jun 23, 2026

Pixel circuit

Inventors: Yu-Chi Hsiao (Hsinchu City, TW); Wen-Chiuan Su (Hsinchu City, TW); Ling-Ying Chien (Hsinchu City, TW); Tsu-Yuan Lin (Hsinchu City, TW); Hung Chi Chen (Hsinchu City, TW); Kuang-Hsiang Liu (Hsinchu City, TW)
Assignee: AUO Corporation
G06F3/0416G09G3/14
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Quick Facts
Patent No.
US 12663892
App. No.
19/232,876
Granted
Jun 23, 2026
Kind
B1
Abstract

A pixel circuit includes a first connection point, a second connection point, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a first capacitor. A first control signal, a second control signal, an emission control signal, a system high voltage, a system low voltage, a first reference voltage, and a second reference voltage received by the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are set to electrically test the first connection point, the second connection point, the first transistor, the second transistor, the third transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the first capacitor.

Claims (41)

1 . A pixel circuit, comprising:

a first connection point configured to connect an anode of a light emitting element;

a second connection point configured to connect a cathode of the light emitting element and coupled to a system low voltage;

a first transistor having a first terminal receiving a system high voltage, a control terminal, and a second terminal;

a second transistor having a first terminal, a control terminal receiving a first control signal, and a second terminal coupled to the second terminal of the first transistor;

a third transistor having a first terminal coupled to the control terminal of the first transistor, a control terminal receiving the first control signal, and a second terminal coupled to the first terminal of the second transistor;

a fourth transistor having a first terminal coupled to the first terminal of the second transistor, a control terminal receiving a second control signal, and a second terminal receiving a first reference voltage;

a fifth transistor having a first terminal providing a data signal, a control terminal receiving the first control signal, and a second terminal;

a sixth transistor having a first terminal coupled to the second terminal of the fifth transistor, a control terminal receiving an emission control signal, and a second terminal receiving the first reference voltage;

a first capacitor coupled between the second terminal of the fifth transistor and the control terminal of the first transistor;

a seventh transistor having a first terminal coupled to the second terminal of the first transistor, a control terminal receiving the emission control signal, and a second terminal coupled to the first connection point;

an eighth transistor having a first terminal coupled to the first connection point, a control terminal receiving the emission control signal, and a second terminal; and

a ninth transistor having a first terminal coupled to the second terminal of the eighth transistor, a control terminal receiving a second reference voltage, and a second terminal coupled to the first terminal of the fifth transistor;

wherein the first control signal, the second control signal, the emission control signal, the system high voltage, the system low voltage, the first reference voltage, and the second reference voltage are set to electrically test the first connection point, the second connection point, the first transistor, the second transistor, the third transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the first capacitor.

2 . The pixel circuit as claimed in claim 1 , wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are respectively P-type transistors.

3 . The pixel circuit as claimed in claim 2 , wherein in response to the second control signal being at a high voltage level, the first control signal being at a low voltage level, the emission control signal being at the low voltage level, the system high voltage being at the low voltage level, the system low voltage being at the low voltage level, the first reference voltage being at the high voltage level, and the second reference voltage being at the high voltage level, the fifth transistor and the sixth transistor form an input path, and the data signal reflects a test result of the input path.

4 . The pixel circuit as claimed in claim 2 , wherein in response to the second control signal being at a high voltage level, the first control signal being at a low voltage level, the emission control signal being at the high voltage level, the system high voltage being at the high voltage level, and the system low voltage being at the low voltage level, the first transistor, the second transistor, the third transistor, the first capacitor, and the fifth transistor form a transistor compensation path, and the data signal reflects a test result of the transistor compensation path.

5 . The pixel circuit as claimed in claim 2 , wherein in response to the second control signal being at a high voltage level, the first control signal being at the high voltage level, the emission control signal being at a low voltage level, the system high voltage being at the low voltage level, the system low voltage being at the high voltage level, and the second reference voltage being at the low voltage level, the data signal reflects a test result of a contact test path formed by the first connection point and the second connection point.

6 . The pixel circuit as claimed in claim 5 , wherein in response to the second control signal being at the high voltage level, the first control signal being at the high voltage level, the emission control signal being at the low voltage level, the system high voltage being at the high voltage level, the system low voltage being at the low voltage level, and the second reference voltage being at the low voltage level, the first transistor and the seventh transistor form a drive path, and the data signal reflects a test result of the drive path.

7 . The pixel circuit as claimed in claim 1 , wherein the light emitting element is a micro light emitting diode.

8 . The pixel circuit as claimed in claim 1 , wherein each of the first connection point and the second connection point is an endpoint of wiring, a through-hole, or a solder joint.

9 . A pixel circuit, comprising:

a first connection point configured to connect an anode of a light emitting element;

a second connection point configured to connect a cathode of the light emitting element and coupled to a system low voltage;

a first transistor having a first terminal receiving a system high voltage, a control terminal, and a second terminal;

a second transistor having a first terminal, a control terminal receiving a first control signal, and a second terminal coupled to the second terminal of the first transistor;

a third transistor having a first terminal coupled to the control terminal of the first transistor, a control terminal receiving the first control signal, and a second terminal coupled to the first terminal of the second transistor;

a fourth transistor having a first terminal coupled to the first terminal of the second transistor, a control terminal receiving a second control signal, and a second terminal receiving a first reference voltage;

a fifth transistor having a first terminal providing a data signal, a control terminal receiving the first control signal, and a second terminal;

a sixth transistor having a first terminal coupled to the second terminal of the fifth transistor, a control terminal receiving an emission control signal, and a second terminal receiving the first reference voltage;

a first capacitor coupled between the second terminal of the fifth transistor and the control terminal of the first transistor;

a seventh transistor having a first terminal coupled to the second terminal of the first transistor, a control terminal receiving the emission control signal, and a second terminal coupled to the first connection point;

an eighth transistor having a first terminal coupled to the first connection point, a control terminal receiving the emission control signal, and a second terminal; and

a ninth transistor having a first terminal coupled to the second terminal of the eighth transistor, a control terminal receiving a second reference voltage, and a second terminal;

wherein the first control signal, the second control signal, the emission control signal, the system high voltage, the system low voltage, the first reference voltage, and the second reference voltage are set to electrically test the first connection point, the second connection point, the first transistor, the second transistor, the third transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the first capacitor.

10 . The pixel circuit as claimed in claim 9 , wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are respectively P-type transistors.

11 . The pixel circuit as claimed in claim 10 , wherein in response to the second control signal being at a high voltage level, the first control signal being at a low voltage level, the emission control signal being at the low voltage level, the system high voltage being at the low voltage level, the system low voltage being at the low voltage level, the first reference voltage being at the high voltage level, and the second reference voltage being at the high voltage level, the fifth transistor and the sixth transistor form an input path, and the data signal reflects a test result of the input path.

12 . The pixel circuit as claimed in claim 10 , wherein in response to the second control signal being at a high voltage level, the first control signal being at a low voltage level, the emission control signal being at the high voltage level, the system high voltage being at the high voltage level, and the system low voltage being at the low voltage level, the first transistor, the second transistor, the third transistor, the first capacitor, and the fifth transistor form a transistor compensation path, and the data signal reflects a test result of the transistor compensation path.

13 . The pixel circuit as claimed in claim 10 , wherein in response to the second control signal being at a high voltage level, the first control signal being at the high voltage level, the emission control signal being at a low voltage level, the system high voltage being at the low voltage level, the system low voltage being at the high voltage level, and the second reference voltage being at the low voltage level, the second end of the ninth transistor provides a test result of a contact test path formed by the first connection point and the second connection point.

14 . The pixel circuit as claimed in claim 13 , wherein in response to the second control signal being at the high voltage level, the first control signal being at the high voltage level, the emission control signal being at the low voltage level, the system high voltage being at the high voltage level, the system low voltage being at the low voltage level, and the second reference voltage being at the low voltage level, the first transistor and the seventh transistor form a drive path, and the second end of the ninth transistor provides a test result of the drive path.

15 . The pixel circuit as claimed in claim 9 , wherein the light emitting element is a micro light emitting diode.