Atomic operations implemented using memory services of data storage devices

1 . A method, comprising:

establishing a connection between a host system and a memory sub-system;

attaching a portion of a random access memory of the memory sub-system as a memory device accessible to the host system over the connection using a first protocol of cache-coherent memory access;

attaching a non-volatile memory of the memory sub-system as a storage device accessible to the host system over the connection using a second protocol of storage access;

setting, in the memory device, a flag indicative of an atomic operation being in progress in the storage device;

executing commands of the atomic operation after the flag is set in the memory device; and

clearing the flag off the memory device after completion of the atomic operation;

wherein the connection is in accordance with a standard of computer express link (CXL).

2 . The method of claim 1 , wherein the method further comprises:

detecting an interruption the executing of the commands of the atomic operation; and

performing an operation of recovery from the interruption, including checking the memory device for the flag.

3 . The method of claim 2 , further comprising:

starting an execution of the commands of the atomic operation in response to a determination, during the operation of recovery from the interruption, that the flag is set in the memory device.

4 . The method of claim 2 , further comprising:

executing a first write command of the atomic operation; and

updating, in the memory device, the flag to indicate completion of the first write command.

5 . The method of claim 4 , wherein the updating is in response to the memory sub-system retrieving the first write command from the host system.

6 . The method of claim 4 , wherein the updating is after the memory sub-system completes an execution of the first write command.

7 . The method of claim 4 , further comprising, in response to a determination, during the operation of recovery from the interruption, that the flag is set in the memory device:

identifying a portion of the commands of the atomic operation being identified as incomplete by the flag; and

starting an execution of the portion of the commands of the atomic operation.

8 . The method of claim 4 , further comprising:

generating, in the memory device and prior to the executing of the first write command of the atomic operation, recovery data usable to undo the executing of the first write command.

9 . The method of claim 8 , wherein the recovery data includes a copy of data at a location being written by the first write command.

10 . The method of claim 8 , wherein the first write command is configured to write at a logical block address; the first write command is executed via remapping the logical block address from a first block of memory cells of the memory sub-system to a second block of memory cells of the memory sub-system, and programming the second block of memory cells to store data written via the first write command; and the recovery data includes an identification of association between the logical block address and the first block of memory cells.

11 . The method of claim 8 , further comprising:

undoing, using the recovery data, the first write command in response to a determination, during the operation of recovery from the interruption, that the flag is set in the memory device.

12 . A memory sub-system, comprising:

a host interface operable on a connection to a host system;

a volatile memory, wherein the memory sub-system is operable to allocate a portion of the volatile memory to provide memory services to the host system over the connection using a first protocol of cache-coherent memory access;

a non-volatile memory operable to provide storage services to the host system over the connection using a second protocol of storage access; and

a controller configured to:

set, in the volatile memory, a flag indicative of an atomic operation being in progress in the non-volatile memory;

executing commands of the atomic operation after the flag is set in the volatile memory; and

clear the flag off the volatile memory after completion of the atomic operation;

wherein the connection is a computer express link (CXL) connection.

13 . The memory sub-system of claim 12 , wherein the host system is configured to store the commands of the atomic operation in the volatile memory using the first protocol of cache-coherent memory access; and the controller is configured to retrieve the commands of the atomic operation from the volatile memory.

14 . The memory sub-system of claim 13 , further comprising:

a backup power source configured to be sufficient to at least allow the controller to continue operations to preserve content in the volatile memory into the non-volatile memory in response to an interruption in an external power supply to the memory sub-system.

15 . The memory sub-system of claim 14 , wherein the controller is further configured to update the flag to indicate completion of a first write command of the atomic operation after an execution of the first write command.

16 . The memory sub-system of claim 15 , wherein the controller is further configured to generate, prior to the execution of the first write command, recovery data usable to undo the execution of the first write command.

17 . The memory sub-system of claim 16 , wherein the controller is configured to:

determine a logical block address of the first write command;

remap the logical block address from a first block of memory cells of the non-volatile memory to a second block of memory cells of the non-volatile memory;

program the second block of memory cells to store data written via the first write command; and

identify, in the recovery data, association between the logical block address and the first block of memory cells.

18 . A non-transitory computer storage medium storing instructions which, when executed in a computing system, cause the computing system to perform a method, comprising:

establishing a connection between a host system of the computing system and a memory sub-system of the computing system;

setting, in a portion of the memory sub-system configured to provide memory services over the connection using a first protocol of cache-coherent memory access, a flag indicative of an atomic operation being in progress in the memory sub-system, before an execution of commands of the atomic operation;

clearing the flag off the portion of the memory sub-system after completion of the atomic operation; and

configuring storage access queues in a memory of the host system.

19 . The non-transitory computer storage medium of claim 18 , wherein the method further comprises:

entering the commands of the atomic operation into the storage access queues after the setting of the flag;

wherein the memory sub-system is configured to access the storage access queues over the connection using a second protocol of storage access.

20 . The non-transitory computer storage medium of claim 19 , wherein the connection is a computer express link (CXL) connection.