IP Library › Granted Patent US 12663938

Granted Patent B2

US 12663938 · App. 17/735,635 · Granted Jun 23, 2026

Memory controller and memory system that executes error correction operation

Inventor: Choung Ki Song (Icheon-si, KR)

Assignee: SK hynix Inc.

G06F3/0655 G06F3/0604 G06F3/0679

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Quick Facts

Patent No.: US 12663938
App. No.: 17/735,635
Granted: Jun 23, 2026
Kind: B2

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Abstract

A memory system may include: a memory device including a plurality of memory cells; and a memory controller configured to store, as a fail address, a first internal address that is generated during a first read operation when at least one memory cell that is accessed during the first read operation among the plurality of memory cells is determined to be a fail, and store, as alternative data, internal read data that is generated during the first read operation.

Claims (75)

1 . A memory system comprising:

a memory device comprising a plurality of memory cells including a first memory cell accessed during a first read operation; and

a memory controller:

configured to store, as a fail address in a fail address storage circuit, a first internal address that is generated during the first read operation when the first memory cell is determined to be a fail;

configured to error correct memory read data from the first memory cell during the first read operation resulting in output error corrected memory read data; and

configured to store, in an alternative data storage circuit when an error flag is activated, internal read data that is generated during the first read operation as alternative data, wherein the error flag is activated when the memory read data contains an error or when an error in the memory read data is corrected;

configured to output the alternative data as the internal read data when the error flag is activated when a second internal address is equal to the fail address during a second read operation executed after the first read operation; and

configured to output the output error corrected memory read data as the internal read data when the error flag is activated when the second internal address is not equal to the fail address during the second read operation;

wherein the memory controller outputs the internal read data to a host through a host interface.

2 . The memory system of claim 1 , wherein the memory controller is configured to output the alternative data as the internal read data when a second internal address, generated during a second read operation that is executed after the first read operation, is equal to the fail address.

3 . The memory system of claim 2 , wherein, when the second internal address is different from the fail address, the memory controller is configured to generate the internal read data based on cell data that is output from at least one memory cell that is accessed by the second internal address.

4 . The memory system of claim 1 , wherein, when a third internal address that is generated during a write operation that is executed after the first read operation is equal to the fail address, the memory controller is configured to store, as the alternative data, internal write data that is generated from host data transmitted from the host.

5 . The memory system of claim 4 , wherein, when the third internal address is different from the fail address, the memory controller is configured to generate memory write data in order to store the internal write data in at least one memory cell that is accessed by the third internal address.

6 . The memory system of claim 1 , wherein the memory controller comprises:

an error correction circuit configured to generate the internal read data and an error flag by executing an error decoding operation based on memory read data; and

a data alternation control circuit configured to store the first internal address as the fail address based on the error flag and configured to store the internal read data as the alternative data.

7 . The memory system of claim 6 , wherein the memory device is configured to generate a cell syndrome from cell data that is output from at least one memory cell that is accessed by the first internal address and configured to transmit the memory read data, composed of the cell data and the cell syndrome, as memory data to the memory controller.

8 . The memory system of claim 7 , wherein the error correction circuit is configured to activate the error flag when an error is contained in the cell data based on the cell syndrome that is included in the memory read data.

9 . The memory system of claim 7 , wherein the error correction circuit is configured to activate the error flag when an error is contained in the cell data and configured to correct the error that is contained in the cell data based on the cell syndrome that is included in the memory read data.

10 . The memory system of claim 6 , wherein the data alternation control circuit comprises a storage control circuit, a match signal generation circuit, and an alternative data storage circuit, wherein the storage control circuit is configured to control the match signal generation circuit to store the first internal address as the fail address when the error flag is activated during the first read operation and configured to control the alternative data storage circuit to store the internal read data as the alternative data when the error flag is activated during the first read operation.

11 . The memory system of claim 6 , wherein the data alternation control circuit comprises a match signal generation circuit configured to store the first internal address as the fail address when the error flag is activated during the first read operation,

wherein the match signal generation circuit is configured to generate a match flag and a match signal by comparing a second internal address to the fail address, the second internal address generated during a data access operation that is executed after the first read operation.

12 . The memory system of claim 11 , wherein the fail address comprises a first fail address and a second fail address,

wherein the match signal generation circuit comprises:

an internal address receiving circuit configured to receive the second internal address;

a fail address storage circuit configured to store the first fail address and the second fail address and configured to generate a first address match signal and a second address match signal by comparing the second internal address to the first fail address and the second fail address; and

a match encoder configured to generate the match flag and the match signal by encoding the first address match signal and the second address match signal.

13 . The memory system of claim 11 , wherein the data alternation control circuit further comprises an alternative data storage circuit configured to store the internal read data as the alternative data when the error flag is activated during the first read operation,

wherein the alternative data storage circuit is configured to transmit the alternative data, selected based on the match signal, as transmission alternative data, to the error correction circuit during the data access operation or configured to store internal write data, transmitted by the error correction circuit, as the transmission alternative data in alternative data that is selected based on the match signal during the data access operation.

14 . The memory system of claim 11 , wherein, during the data access operation, the error correction circuit is configured to receive the alternative data as transmission alternative data from the match signal generation circuit based on the match flag and configured to output the transmission alternative data as the internal read data.

15 . The memory system of claim 14 , wherein the error correction circuit is configured to transmit internal write data, generated from host data that is transmitted from the host based on the match flag, as the transmission alternative data, to the match signal generation circuit during the data access operation,

wherein the match signal generation circuit is configured to store the transmission alternative data as the alternative data.

16 . A memory controller comprising:

an error correction circuit configured to generate internal read data and an error flag by executing an error decoding operation on memory read data including cell data and a cell syndrome output from a first memory cell of a plurality of memory cells included in a memory device, which first memory cell is accessed during a first read operation and configured to error correct memory read data from the first memory cell during the first read operation resulting in output error corrected memory read data;

a data alternation control circuit configured to:

store, in a fail address storage circuit, a first internal address of the first memory cell, generated during the first read operation, as a fail address based on the error flag;

store, in an alternative data storage circuit, the internal read data as alternative data, wherein the error flag is activated when the memory read data contains an error or when an error in the memory read data is corrected;

a read data queue configured to output the internal read data to a host through a host interface.

17 . The memory controller of claim 16 , wherein, based on the cell syndrome that is included in the memory read data, the error correction circuit is configured to activate the error flag when an error is contained in the cell data.

18 . The memory controller of claim 16 , wherein, based on the cell syndrome that is included in the memory read data, the error correction circuit is configured to activate the error flag when an error is contained in the cell data and the error that is contained in the cell data is corrected.

19 . The memory controller of claim 16 , wherein the data alternation control circuit comprises a storage control circuit, a match signal generation circuit, and an alternative data storage circuit,

wherein the storage control circuit is configured to control the match signal generation circuit to store the first internal address as the fail address when the error flag is activated during the first read operation and configured to control the alternative data storage circuit to store the internal read data as the alternative data, when the error flag is activated during the first read operation.

20 . The memory controller of claim 16 , wherein the data alternation control circuit comprises a match signal generation circuit configured to store the first internal address as the fail address when the error flag is activated during the first read operation,

21 . The memory controller of claim 20 , wherein the fail address comprises a first fail address and a second fail address,

wherein the match signal generation circuit comprises:

an internal address receiving circuit configured to receive the second internal address;

a match encoder configured to generate the match flag and the match signal by encoding the first address match signal and the second address match signal.

22 . The memory controller of claim 20 , wherein the data alternation control circuit further comprises an alternative data storage circuit configured to store the internal read data as the alternative data when the error flag is activated during the first read operation,

23 . The memory controller of claim 20 , wherein, during the data access operation, the error correction circuit is configured to receive the alternative data as transmission alternative data from the match signal generation circuit based on the match flag and configured to output the transmission alternative data as the internal read data.

24 . The memory controller of claim 20 , wherein the error correction circuit is configured to transmit internal write data, generated from host data that is transmitted from the host based on the match flag, as the transmission alternative data, to the match signal generation circuit during the data access operation,

wherein the match signal generation circuit is configured to store the transmission alternative data as the alternative data.

25 . A memory system comprising:

a memory device comprising a plurality of memory cells including a first memory cell; and

a memory controller comprising:

an event signal generation circuit configured to generate an event signal;

a self command generation circuit configured to generate a self command for a self read operation in response to activation of the event signal;

a self address generation circuit configured to generate a self address for the self read operation in response to activation of the event signal; and

an error correction circuit configured to, during the self read operation, generate internal read data and an error flag by executing an error decoding operation on memory read data including cell data and configured to error correct memory read data from the first memory cell during the first read operation resulting in output error corrected memory read data, wherein the error flag is activated when the memory read data contains an error or when an error in the memory read data is corrected; and

a data alternation control circuit:

configured to store the self address as a fail address in a fail address storage circuit based on the error flag when the first memory cell is determined to be a fail during the self read operation;

configured to store, in an alternative data storage circuit when the error flag is activated, the internal read data generated during the self read operation as alternative data;

configured to output the alternative data as internal read data when the error flag is activated when a second internal address is equal to the fail address during a second read operation executed after the first read operation;

a read data queue configured to output the internal read data to a host through a host interface.

26 . The memory system of claim 25 , wherein the first memory cell is determined to be a fail when an error is detected in the first memory call.

27 . The memory system of claim 25 , wherein the self command comprises an identification bit distinguished from a host command from the host.

28 . The memory system of claim 25 , wherein output of the the alternative data blocks access of an error in the first memory cell.

29 . The memory system of claim 25 , wherein the memory controller is configured to, when the alternative data is output as the internal read data, block an error from the first memory cell that is determined to be a fail.

30 . The memory controller of claim 16 , further configured to, when the alternative data is output as the internal read data, block an error from the first memory cell that is determined to be a fail.

31 . The memory system of claim 1 , wherein the memory controller is configured to, when the alternative data is output as the internal read data, block an error from the first memory cell that is determined to be a fail.