Information processing circuit and method of designing information processing circuit

1 . An information processing circuit, that performs operations on layers in deep learning, the information processing circuit comprising:

a product sum circuit configured to perform a product-sum operation using input data and parameter values,

a parameter value output circuit configured to output the parameter values, and

a number of basic circuits corresponding to a number of parallel processes,

wherein the parameter value output circuit comprises a combinational circuit, and

wherein each of a plurality of the basic circuits includes the product sum circuit and the parameter value output circuit.

2 . The information processing circuit according to claim 1 , wherein

the basic circuit has a layer-specific circuit configuration, and

the parameter value output circuit outputs the parameters whose values are fixed.

3 . A method of designing an information processing circuit configured to perform operations on layers in deep learning, the method comprising:

inputting data for identifying learned parameter values and a network structure;

generating a product sum circuit configured to perform a product-sum operation using input data and the parameter values, and specializing in a layer in the network structure;

generating a combinational circuit configured to output the multiple parameter values; and

generating a number of basic circuits each including the product sum circuit and a parameter value output circuit which outputs the parameter values, wherein the number of basic circuits corresponds to a number of parallel processes.

4 . The method of claim 3 , wherein, based on the deep learning being realized with multiple layers, the product sum circuit for each layer and the combinational circuit for each layer are generated.

5 . The method of claim 3 , further comprising:

determining a parallel degree according to a calculation speed required to each layer; and

generating a number of the product sum circuits depending on the parallel degree.

6 . The method of claim 3 , further comprising:

changing one or more parameter values among input multiple parameter values so that the parameter values of the same value increase.

7 . The method of claim 3 , further comprising:

changing one or more parameter values among input multiple parameter values so that a pattern with the parameter values appears in succession.

8 . The method of claim 6 , further comprising:

measuring accuracy of the information processing circuit;

estimating a circuit area of the combinational circuit; and

changing the parameter values repeatedly until the accuracy of the information processing circuit is greater than or equal to a first reference value, and the circuit area of the combinational circuit is less than or equal to a second reference value.

9 . The method of designing an information processing circuit according to claim 3 , wherein

the basic circuit has a layer-specific circuit configuration, and

the parameter value output circuit is configured to output the parameters whose values are fixed.

10 . An information processing circuit designing device which generates the information processing circuit configured to perform operations on layers in deep learning, the information processing circuit designing device comprising:

an input unit configured to input data for identifying learned parameter values and a network structure;

a calculator generator configured to generate a product sum circuit configured to perform a product-sum operation using input data and the parameter values, and specializing in a layer in the network structure;

a parameter value output circuit generator configured to generate a combinational circuit configured to output the multiple parameter values; and

a basic circuit generator configured to generate a number of basic circuits corresponding to the number of parallel processes, each of the basic circuits including the product sum circuit and a parameter value output circuit configured to output the parameter values.

11 . The information processing circuit designing device according to claim 10 , wherein

based on the deep learning being realized with multiple layers, the calculator generator is further configured to generate the product sum circuit for each layer and the parameter value output circuit generator is further configured to generate the combinational circuit for each layer.

12 . The information processing circuit designing device according to claim 10 , further comprising:

a parallel degree determination unit configured to determine a parallel degree according to a calculation speed required to each layer,

wherein the calculator generator is further configured to generate a number of the product sum circuits depending on the parallel degree.

13 . The information processing circuit designing device according to claim 10 , further comprising:

a parameter optimization unit configured to change one or more parameter values among input multiple parameter values so that the parameter values of the same value increase.

14 . The information processing circuit designing device according to claim 10 , wherein

the basic circuit has a layer-specific circuit configuration, and

the parameter value output circuit is configured to output the parameters whose values are fixed.