IP Library Granted Patent US 12,663,970
Granted Patent B2
US 12,663,970 · App. 17/692,425 · Granted Jun 23, 2026

Data parallel programming task graph optimization through device telemetry

Inventors: Michael Kinsner (Halifax, CA); Ben J. Ashbaugh (Folsom, CA); James Brodman (Marlborough, MA); Rajesh Poornachandran (Portland, OR)
Assignee: INTEL CORPORATION
G06F8/4441G06F8/433G06F9/4881
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Quick Facts
Patent No.
US 12,663,970
App. No.
17/692,425
Granted
Jun 23, 2026
Kind
B2
Abstract

An apparatus to facilitate data parallel programming task graph optimization through device telemetry is disclosed. The apparatus includes a processor to: receive, from a compiler, compiled code generated from source code of an application, the compiled code to support a workload of the application; generate a task graph of the application using the compiled code, the task graph to represent at least one of a relationship or dependency of the compiled code; receive runtime telemetry data corresponding to execution of the compiled code on the one or more accelerator devices; identify one or more scheduling optimizations for the one or more accelerator devices based on the task graph and the received telemetry data; and provide a scheduling command to cause the one or more scheduling optimizations to be implemented in the one or more accelerator devices.

Claims (44)

1 . An apparatus comprising:

a processor to:

receive, from a compiler, compiled code generated from source code of an application, wherein the compiled code is to support a workload of the application;

generate a task graph of the application using the compiled code, wherein the task graph of the application is to represent at least one of a relationship or a dependency of the compiled code;

issue first scheduling commands to cause first scheduling operations to be executed on one or more hardware accelerator devices, wherein the first scheduling operations are to cause the one or more hardware accelerator devices to execute the compiled code, and wherein the one or more hardware accelerator devices are to produce runtime telemetry data resulting from the execution of the compiled code on the one or more hardware accelerator devices;

receive the runtime telemetry data corresponding to the execution of the compiled code on the one or more hardware accelerator devices;

train, using the received runtime telemetry data, a scheduler optimizer to identify updates to the first scheduling operations based on the task graph of the application and the received runtime telemetry data, wherein the updates to the first scheduling operations are to reduce latency and power consumption corresponding to the one or more hardware accelerator devices and the application;

generate, using the scheduler optimizer, revised scheduling operations based on the updates to the first scheduling operations, wherein the revised scheduling operations comprise an execution ordering of invocations of kernels of the application and data movements of the application;

issue revised scheduling commands to cause the revised scheduling operations to be executed on the one or more hardware accelerator devices; and

execute the revised scheduling commands on the one or more hardware accelerator devices to optimize the execution of the compiled code.

2 . The apparatus of claim 1 , wherein the received runtime telemetry data is generated during an offline harvesting session comprising a pre-execution of the application prior to a live execution of the application.

3 . The apparatus of claim 1 , wherein the received runtime telemetry data is generated during an online harvesting session comprising a live execution of the application.

4 . The apparatus of claim 1 , wherein the received runtime telemetry data is cached for future executions of the application.

5 . The apparatus of claim 1 , wherein the revised scheduling operations comprise a selection of the one or more hardware accelerator devices to execute the kernels of the application.

6 . The apparatus of claim 1 , wherein the scheduler optimizer is trained to identify the updates to the first scheduling operations through utilization of one or more of statistical techniques, machine learning/deep learning, or energy-minimizing optimization techniques.

7 . The apparatus of claim 1 , wherein the received runtime telemetry data comprises at least one of power consumption, cache access efficiencies, hardware utilization, raw memory utilization, performance per watt, performance per clock cycle, time duration of execution, interconnect efficiency, or occurrence of stalls.

8 . The apparatus of claim 1 , wherein the one or more hardware accelerator devices comprise at least one of a graphic processing unit (GPU), a central processing unit (CPU), or a programmable integrated circuit (IC).

9 . The apparatus of claim 8 , wherein the programmable IC comprises at least one of a field programmable gate array (FPGA), a programmable array logic (PAL), a programmable logic array (PLA), a field programmable logic array (FPLA), an electrically programmable logic device (EPLD), an electrically erasable programmable logic device (EEPLD), a logic cell array (LCA), or a complex programmable logic device (CPLD).

10 . A method comprising:

receiving, by a processing device and from a compiler, compiled code generated from source code of an application, wherein the compiled code is to support a workload of the application;

generating, by the processing device, a task graph of the application using the compiled code, wherein the task graph of the application is to represent at least one of a relationship or a dependency of the compiled code;

issuing, by the processing device, first scheduling commands to cause first scheduling operations to be executed on one or more hardware accelerator devices, wherein the first scheduling operations are to cause the one or more hardware accelerator devices to execute the compiled code, and wherein the one or more hardware accelerator devices are to produce runtime telemetry data resulting from the execution of the compiled code on the one or more hardware accelerator devices;

receiving, by the processing device, the runtime telemetry data corresponding to the execution of the compiled code on the one or more hardware accelerator devices;

training, by the processing device and using the received runtime telemetry data, a scheduler optimizer to identify updates to the first scheduling operations based on the task graph of the application and the received runtime telemetry data, wherein the updates to the first scheduling operations are to reduce latency and power consumption corresponding to the one or more hardware accelerator devices and the application;

generating, by the processing device and using the scheduler optimizer, revised scheduling operations based on the updates to the first scheduling operations, wherein the revised scheduling operations comprise an execution ordering of invocations of kernels of the application and data movements of the application;

issuing, by the processing device, revised scheduling commands to cause the revised scheduling operations to be executed on the one or more hardware accelerator devices; and

executing, by the processing device, the revised scheduling commands on the one or more hardware accelerator devices to optimize the execution of the compiled code.

11 . The method of claim 10 , wherein the received runtime telemetry data is generated during an offline harvesting session comprising a pre-execution of the application prior to a live execution of the application.

12 . The method of claim 10 , wherein the revised scheduling operations comprise a selection of the one or more hardware accelerator devices to execute the kernels of the application.

13 . The method of claim 10 , further comprising training the scheduler optimizer to identify the updates to the first scheduling operations through utilization of one or more of statistical techniques, machine learning/deep learning, or energy-minimizing optimization techniques.

14 . The method of claim 10 , wherein the received runtime telemetry data comprises at least one of power consumption, cache access efficiencies, hardware utilization, raw memory utilization, performance per watt, performance per clock cycle, time duration of execution, interconnect efficiency, or occurrence of stalls.

15 . A non-transitory machine-readable storage medium storing instructions that, when executed by at least one processor, cause the at least one processor to at least:

receive, by the at least one processor and from a compiler, compiled code generated from source code of an application, wherein the compiled code is to support a workload of the application;

generate, by the at least one processor, a task graph of the application using the compiled code, wherein the task graph of the application is to represent at least one of a relationship or a dependency of the compiled code;

issue, by the at least one processor, first scheduling commands to cause first scheduling operations to be executed on one or more hardware accelerator devices, wherein the first scheduling operations are to cause the one or more hardware accelerator devices to execute the compiled code, and wherein the one or more hardware accelerator devices are to produce runtime telemetry data resulting from the execution of the compiled code on the one or more hardware accelerator devices;

receive, by the at least one processor, the runtime telemetry data corresponding to the execution of the compiled code on the one or more hardware accelerator devices;

train, by the at least one processor and using the received runtime telemetry data, a scheduler optimizer to identify updates to the first scheduling operations based on the task graph of the application and the received runtime telemetry data, wherein the updates to the first scheduling operations are to reduce latency and power consumption corresponding to the one or more hardware accelerator devices and the application;

generate, by the at least one processor and using the scheduler optimizer, revised scheduling operations based on the updates to the first scheduling operations, wherein the revised scheduling operations comprise an execution ordering of invocations of kernels of the application and data movements of the application;

issue, by the at least one processor, revised scheduling commands to cause the revised scheduling operations to be executed on the one or more hardware accelerator devices; and

execute, by the at least one processor, the revised scheduling commands on the one or more hardware accelerator devices to optimize the execution of the compiled code.

16 . The non-transitory machine-readable storage medium of claim 15 , wherein the received runtime telemetry data is generated during an offline harvesting session comprising a pre-execution of the application prior to a live execution of the application.

17 . The non-transitory machine-readable storage medium of claim 15 , wherein the revised scheduling operations comprise a selection of the one or more hardware accelerator devices to execute the kernels of the application.

18 . The non-transitory machine-readable storage medium of claim 15 , wherein the scheduler optimizer is trained to identify the updates to the first scheduling operations through utilization of one or more of statistical techniques, machine learning/deep learning, or energy-minimizing optimization techniques.

19 . The non-transitory machine-readable storage medium of claim 15 , wherein the received runtime telemetry data comprises at least one of power consumption, cache access efficiencies, hardware utilization, raw memory utilization, performance per watt, performance per clock cycle, time duration of execution, interconnect efficiency, or occurrence of stalls.