Compiling device and method for performance speed-up of a program
Provided are a compiling device, a compiling method, and a compiling program with which the speed of a program can be increased when a loop in a program includes an access to adjacent data. The compiling device includes: a loop analysis unit for determining whether vectorization of a loop in a source program is possible when an access to adjacent data is included in the loop; and a vectorization execution unit for generating an instruction for reading elements required for computation from a memory to a vector register when access to the adjacent data is included and the vectorization of the loop is possible.
1 . A compiling device comprising:
at least one memory configured to store instructions; and
at least one processor configured to execute the instructions to:
determine whether vectorization of a loop of a source program is possible when an access to adjacent data is included in the loop of the source program,
generate a vector load instruction to read an element required for computation from a memory to a vector register when the access to the adjacent data is included in the loop of the source program and the vectorization of the loop of the source program is possible,
generate a vector element shift instruction that generates vector data obtained by shifting an element read into the vector register,
generate a vector computation instruction to execute a computation,
generate a vector store instruction to write a computation result from the vector register to the memory, and
execute the vector element shift instruction without reducing vector length, which provides efficient execution of the computation,
wherein when a value of a subscript of an adjacent array element increases, the at least one processor shifts data of a specified first vector register to the left by an amount of the increase in the value of the subscript of the adjacent array element and substitutes the data of the specified first vector register into a second vector register, and further combines data from a head element of a next vector register to a tail element by a same amount as the amount of the increase in the value of the subscript of the adjacent array element.
2 . The compiling device according to claim 1 , wherein:
when a value of a subscript of an adjacent array element decreases, the at least one processor shifts data of a specified first vector register to the right by an amount of the decrease in the value of the subscript of the adjacent array element and substitutes the data of the specified first vector register into a second vector register, and further combines data from a head element of a next vector register to a head element by a same amount as the amount of the decrease in the value of the subscript of the adjacent array element.
3 . The compiling device according to claim 2 , wherein:
the at least one processor recognizes whether access to adjacent data is included in a loop, and determines whether a loop including access to adjacent data is vectorizable.
4 . The compiling device according to claim 1 , wherein:
the at least one processor recognizes whether access to adjacent data is included in a loop, and determines whether a loop including access to adjacent data is vectorizable.
5 . A compiling method performed by a computer and comprising:
when access to adjacent data is included in a loop of a source program, determining whether the loop of the source program can be vectorized;
generating a vector load instruction to read an element required for computation from a memory to a vector register when the access to the adjacent data is included in the loop of the source program and the loop of the source program is vectorizable;
generating a vector element shift instruction that generates vector data obtained by shifting an element read into the vector register;
generating a vector computation instruction to execute a computation;
generating a vector store instruction to write a computation result from the vector register to the memory; and
executing the vector element shift instruction without reducing vector length, which provides efficient execution of the computation,
wherein when a value of a subscript of an adjacent array element increases, the vector element shift instruction shifts data of a specified first vector register to the left by an amount of the increase in the value of the subscript of the adjacent array element and substitutes the data of the specified first vector register into a second vector register, and further combines data from a head element of a next vector register to a tail element by a same amount as the amount of the increase in the value of the subscript of the adjacent array element.
6 . The compiling method according to claim 5 , wherein:
when a value of a subscript of an adjacent array element decreases, shifting data of a specified first vector register to the right by an amount of the decrease in the value of the subscript of the adjacent array element and substituting the data of the specified first vector register into a second vector register, and further combining data from a head element of a next vector register to a head element by a same amount as the amount of the decrease in the value of the subscript of the adjacent array element.
7 . A non-transitory program recording medium storing a compiling program executable on a computer to perform processing comprising:
determining whether vectorization of a loop of a source program is possible when an access to adjacent data is included in the loop of the source program;
generating a vector load instruction to read an element required for computation from a memory to a vector register when the access to the adjacent data is included in the loop of the source program and the vectorization of the loop of the source program is possible;
generating a vector element shift instruction that generates vector data obtained by shifting an element read into the vector register;
generating a vector computation instruction to execute a computation;
generating a vector store instruction to write a computation result from the vector register to the memory; and
executing the vector element shift instruction without reducing vector length, which provides efficient execution of the computation,
wherein when a value of a subscript of an adjacent array element increases, the vector element shift instruction shifts data of a specified first vector register to the left by an amount of the increase in the value of the subscript of the adjacent array element and substitutes the data of the specified first vector register into a second vector register, and further combines data from a head element of a next vector register to a tail element by a same amount as the amount of the increase in the value of the subscript of the adjacent array element.
8 . The non-transitory program recording medium according to claim 7 , wherein the processing further comprises:
when a value of a subscript of an adjacent array element decreases, shifting data of a specified first vector register to the right by an amount of the decrease in the value of the subscript of the adjacent array element and substituting the data of the specified first vector register into a second vector register, and further combining data from a head element of a next vector register to a head element by a same amount as the amount of the decrease in the value of the subscript of the adjacent array element.
9 . The non-transitory program recording medium according to claim 8 , wherein the processing further comprises:
recognizing whether access to adjacent data is included in a loop; and
determining whether a loop including access to adjacent data is vectorizable.
10 . The non-transitory program recording medium according to claim 7 , wherein the processing further comprises:
recognizing whether access to adjacent data is included in a loop; and
determining whether a loop including access to adjacent data is vectorizable.