Memory patching with associative and directly mapped patch data

1 . A method for patching a boot read-only memory, ROM, comprising:

receiving, from a bus controller, a request for first data stored at a first address in a first portion of an address map of the boot ROM;

determining, based on the first address, that an associative record in a first region of a one-time programmable, OTP, memory includes an address that matches the first address;

returning, to the bus controller, patch data of the associative record, the patch data including a jump instruction to a second address in a second portion of the address map of the boot ROM, the second portion of the address map being distinct from the first portion of the address map;

receiving, from the bus controller and based on the patch data, a request for second data stored at the second address in the second portion of the address map, the addresses in the second portion of the address map being directly mapped to records in a second region of the OTP memory;

accessing, based on an offset between the start of the second portion of the address map and the second address, the second data of a directly mapped record in the second region of the OTP memory, the offset based on a header record of the OTP memory that stores a value describing a quantity of associative records in the first region of the OTP memory; and

returning, to the bus controller, the second data of the directly mapped record from the OTP memory.

2 . The method of claim 1 , wherein the offset is further based on:

a quantity of associative records stored in the first region of the OTP memory; and

the second address in the second portion of the address map of the boot ROM.

3 . The method of claim 2 , wherein the header record of the OTP memory includes a value that describes the quantity of associative records stored in the programmable memory.

4 . The method of claim 1 , wherein the second address indicates a value that corresponds to a quantity of directly mapped records between a first directly mapped record in the second region of the OTP memory and the directly mapped record in the OTP memory storing the second data.

5 . The method of claim 1 , wherein the directly mapped records of the second portion region of the OTP memory:

do not include an address field; or

do not include information related to addresses of the second portion of the address map of the boot ROM.

6 . The method of claim 1 , wherein the boot ROM does not include data stored at the second address in the second portion of the boot ROM address map.

7 . The method of claim 1 , wherein:

the request for the first data is issued by a boot loader to the bus controller, the request is received via a data bus, the request is a request for boot code, and the method further comprises:

sending, via the data bus, the second data as patch data to the boot loader as a response to the request for the first data.

8 . The method of claim 1 , wherein:

the request for first data stored is a request for boot code stored in the boot ROM; and

the second data comprises patch data that includes one of:

instructions to execute before boot code stored in the boot ROM that corresponds to one or more other addresses in the address map after the first address; or

instructions to execute in place of boot code stored in the boot ROM that corresponds to one or more other addresses in the address map after the first address.

9 . The method of claim 1 , wherein the records in the second region of the OTP memory are in a same region, the method further comprising:

setting a remaining space in the second region of the OTP memory to a locked state, wherein the remaining space is unavailable for further modification; and

locking the second region portion of the OTP memory with one or more of a lock bit or a security register setting.

10 . The method of claim 1 , wherein the returning, to the bus controller, of the second data of the directly mapped record in the second region of the OTP memory comprises:

determining, by an OTP controller, one or more lines of the second data to be returned; and

returning, by the OTP controller, the one or more lines of the second data to the bus controller.

11 . The method of claim 1 , wherein the directly mapped records do not comprise an associative address field.

12 . An apparatus, comprising:

a boot read-only memory, ROM;

a one-time programmable, OTP, memory;

a patch manager; and

a ROM controller configured to:

receive, from a bus controller, a request for first data stored at a first address in a first portion of an address map of the boot ROM;

return to the bus controller, based on a determination by the patch manager that an associative record in a first region of the OTP memory includes an address that matches the first address, patch data of the associative record, the patch data including a jump instruction to a second address in a second portion of the address map of the boot ROM, the second portion of the address map being distinct from the first portion of the address map;

receive, from the bus controller and based on the patch data, a request for second data stored at the second address in the second portion of the address map, the addresses in the second portion of the address map being directly mapped to records in a second region of the OTP memory;

receive, from the patch manager, the second data from a directly mapped record in the second region of the OTP memory, the patch manager configured to access the directly mapped records in the second region of the OTP memory based on an offset between the start of the second portion of the address map and the second address, the offset based on a header record of the OTP memory that stores a value describing a quantity of associative records in the first region of the OTP memory; and

return, to the bus controller, the second data of the directly mapped record in the second region of the OTP memory.

13 . The apparatus of claim 12 , wherein the directly mapped records of the OTP memory:

do not include an address field; or

do not include information related to addresses of the second portion of the address map of the boot ROM.

14 . The apparatus of claim 12 , wherein:

addresses in the second portion of the address map of the boot ROM are offset from addresses in the first portion of the address map of the boot ROM; and

the boot ROM does not include rows or lines of boot code that map to the addresses in the second portion of the boot ROM address map.

15 . The apparatus of claim 12 , wherein the ROM controller is further configured to:

receive, via a data bus, the request for the first data stored at the first address in the first portion of the address map of the boot ROM as a request for boot code from a boot loader; and

return, via the data bus, the patch data to the boot loader as a response to the request for the first data.

16 . A non-transitory computer readable storage medium comprising computer-executable instructions that when executed by a computer will cause the computer to: receive, from a bus controller, a request for first data stored at a first address in a first portion of an address map of a boot ROM; determine, based on the first address, that an associative record in a first region of a one-time programmable, OTP, memory includes an address that matches the first address; return, to the bus controller, patch data of the associative record, the patch data including a jump instruction to a second address in a second portion of the address map of the boot ROM, the second portion of the address map being distinct from the first portion of the address map; receive, from the bus controller and based on the patch data, a request for second data stored at the second address in the second portion of the address map, the addresses in the second portion of the address map being directly mapped to records in a second region of the OTP memory; access, based on an offset between the start of the second portion of the address map and the second address, the second data of a directly mapped record in the second region of the OTP memory, the offset based on a header record of the OTP memory that stores a value describing a quantity of associative records in the first region of the OTP memory; and return, to the bus controller, the second data of the directly mapped record from the OTP memory.

17 . The non-transitory computer readable storage medium of claim 16 , wherein the offset is based on: a quantity of associative records stored in the first region of the OTP memory; and the second address in the second portion of the address map of the boot ROM.

18 . The non-transitory computer readable storage medium of claim 17 , wherein the header record of the OTP memory includes a value that describes the quantity of associative records stored in the OTP memory.

19 . The non-transitory computer readable storage medium of claim 16 , wherein the second address indicates a value that corresponds to a quantity of directly mapped records between a first directly mapped record in the second region of the OTP memory and the directly mapped record in the OTP memory storing the second data.

20 . The non-transitory computer readable storage medium of claim 16 , wherein the computer-executable instructions further cause the computer to access third data stored at a third address in the second portion of the address map of the boot ROM, the third data including another jump instruction, the other jump instruction including a fourth address in the first portion of the address map.